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A Rapid Prototyping Environment for Teaching
Digital Logic Design

Andrej Zemva, Member IEEE, Andrej Trost, Student Member, IEEE, and Baldomir Zajc, Member IEEE

Abstract - In this paper, we present a rapid prototyping environment for teaching digital logic design. Our primary goal was to build an FPGA based hardware prototyping system that provides sufficient flexibility for the implementation and functional verification of various digital circuit designs. Since the system is intended to be used as an experimental and demonstration board to support digital design courses and practices for the undergraduate students, it is simple to use and completely supported by the software for automatic implementation of digital circuits.

The prototyping environment consists of a PC and the programmable board composed of 3 FPGAs. One FPGA is used to implement the digital circuit, while the rest of the devices implement an interface between the digital circuit and the PC. The PC is used for designing a digital circuit, automatic generation of the interface logic, programming the FPGAs and as a test engine for functional verification of the designed circuit. The presented environment is used in the regular educational process and the sample student projects are summarized.

I. Introduction

A typical approach to design a large digital system is divided into several phases. The process usually begins with the product requirements which evolve first into a general design specification. Utilizing software support for high-level synthesis, logic synthesis and optimization, circuit simulation, technology mapping and layout synthesis, the design is derived into a functional equivalent circuit that can be readily implemented as a physical design [1]. The design cycle ends with the physical implementation, circuit verification and integration into the environment.

With the computational power of the todays computers and advances in EDA (Electronic Design Automation), the design cycle time is enormously reduced. However, until the first appearance of Field Programmable Gate Arrays (FPGAs) in the mid-eighties [2], a certain gap between the circuit design phase and the circuit implementation phase existed. Implementation in a mask-programmable technology such as mask-programmable gate arrays or standard cells typically requires extensive manufacturing efforts that result in a high cost and relatively long implementation period of several weeks.

User-programmability that is built into FPGAs significantly reduces the time and the cost of the prototyping realization and allows fast re-design that is often imposed with the design errors in one design cycle. Another important aspect of FPGAs is that the designer can implement a circuit by himself, and thus complete the whole design process from the initial circuit specification to the physical implementation and system integration in one place. This is especially important for educational purposes. For example, circuit design practice courses at universities are often constrained with the tight time frames and limited financial budget which may prevent students completing large ASIC design unless FPGA technology is used. Through the complete design process, which ends with the working implementations, students get insight into each step of design cycle and some specific problems that occur with the prototyping realization, functional verification and integration of the design into the existed system.

We first motivate and present basic requirements and objectives that have been evaluated in the presented prototyping environment. Developed hardware and software are presented next. In the last two sections, we discuss implementations of some real designs, our experiences and directions for the future work.

II. Hardware Prototyping Environment

A. Motivation

Our primary goal was to build an FPGA based hardware prototyping system and a general-purpose fully user-programmable environment that provides sufficient flexibility for the implementation and functional verification of various types of designs. Since the system is intended to be used mainly as an educational experimental and demonstration board to support digital design courses and practices of undergraduate students, it should provide an implementation of digital circuits with the logic complexity up to 10.000 equivalent logic gates. We consider a typical user to be a relatively inexperienced designer, with no specific knowledge of design automation and related problems such as component placement, routing, partitioning, verification methods, etc. Thus, the system is designed to be easy to use and completely supported by the software for automatic implementation on the prototyping board.

B. Basic Hardware Components

We follow some useful hints and requirements given in [3] and [4]. Fig. 1 illustrates the prototyping environment consisting of a host PC computer, a programmable hardware board with 3 Xilinx XC3000 FPGAs [5] and an external board. A PC computer is used here as:


Fig. 1: Basic hardware in a prototyping system.

We built a relatively small and simple programmable prototyping board consisting of one Xilinx XC3195, assigned as LCA2, and two XC3042 FPGA devices, assigned as LCA1 and LCA3. The largest device, LCA2, is mainly used to implement a designed circuit, while the rest of the devices implement an interface controller which connects the prototyping board to the external memory and to the PC bus. As shown in Fig. 1, each of the LCA1 and LCA3 devices is connected with 72-bit wide datapaths to the LCA2, covering together all 144 user I/O pins of the LCA2. Since the interface controller utilizes relatively small portion of both FPGA devices, we lock I/O locations at these FPGA devices according to the connections to the LCA2. We give a more detailed description of the interface controller later on. The programmable board is connected with a 24-bit wide datapath to the host PC computer which provides parallel communication with 16 data lines, 4 address lines and 4 control lines. A 144 pin connector around the LCA2 is used to provide access to all user I/O signals and to connect additional external boards. An example of the external I/O card is shown in Fig. 1. It consists of a 128k x 16 static RAM, a clock generator, a debounced keyboard and a display. Since the FPGA board is intended to serve also as a standalone demonstration board, additional EPROM may hold the configuration data for master-mode programming of the daisy-chained FPGA devices.

Xilinx FPGA devices are selected due to their reprogrammability. The main reason for designing such a prototyping board with the given FPGA devices and datapaths relies on the requirement that the implementation of the designed circuit should be automatic with as few manual interactions as possible. For the design implemented in the LCA2 device, we very loosely restrict place and route software (XACT APR) [6] to efficiently and automatically complete the implementation. This improves the routability and consequently the average CLB utilization that can be achieved in the largest device. Specifically, when the external memory is used for verification, we prohibit the use only of those I/O pin locations of the LCA2 device that share data lines with address and control bus of the external card. The use of the external memory provides standalone operation of the programmable board without data exchange to the host computer during the computation. External I/O card can be used in two different ways: as an extension card for application purposes or, during the functional verification, as a memory for storing the test vectors and intermediate results. Consequently, it speeds up the functional verification, since the speed of the data exchange between the external RAM and the programmable board is usually greater than the data exchange between the PC computer and the board.

C. Interface controller

Here, we present the controller as it is used during the functional verification phase. In this phase, it controls the transfer of test vectors and test results between all three main parts of the prototyping system. First, the interface controller controls the communication between the PC and the external memory. In the next phase, the PC passes control to the controller on board and the programmable board is operating standalone. The main task of the controller during this phase is to transfer the test vectors stored in the external memory to the inputs of the LCA2 and to transfer the obtained output signals of the designed circuit back to the external memory. Due to the different width of the datapaths at the host PC/RAM side and the LCA2 side, the interface controller performs additional multiplexing/demultiplexing of data lines. The interface controller also arbitrates memory access and generates additional control signals for correct data transfer. Once the functional verification is completed, the interface controller communicates with the PC for transferring the data from the external memory back to the host PC. Optionally, the interface controller can be designed to directly transfer data between the host PC and the implemented circuit without the use of the external memory. This may be particularly useful for verifying the designed circuit with higher I/O requirement, where we gain additional 17 user I/O pins of the LCA2.


Fig. 2: Block diagram of the interface controller.

An architectural view of the interface controller implemented for the purpose of functional verification is shown in Fig. 2. Although the configuration of the controller is flexible, it has an overall structure consisting of 4 main blocks: a fixed 16-bit wide I/O host data register connected to the host PC/RAM data bus, control unit, multiplexor/demultiplexor logic and the I/O peripheral data register with the flexible size connected to the LCA2 datapath. The control unit consists of the main process controller and the data path selector. The main process controller generates correct addresses, control signals for memory read and write operations, and control signals for latching data at the host and LCA2 side. The data path selector sets the select lines of the multiplexor/demultiplexor logic to transfer data between I/O host data register and the host PC/RAM data bus. Once the test vectors and results are stored in the memory, the select lines are set internally by the main process controller. Optionally, when the data need to be transferred directly between the PC and LCA2, select lines are set by the additional address lines coming from the host PC.

In general, the configuration of the interface controller depends on the design being implemented in LCA2 and the integration of the design into the environment. Therefore, the interface controller should be specifically designed for each new application. For that purpose, we have written an automatic generator of the interface controller, as described in the next section.

III. Software support for the functional verification

The design flowchart of the circuit to be implemented is illustrated in Fig. 3. The design entry is either schematic or behavioral (VHDL). The initial description is synthesized using SIS [7] or compiled using Viewlogic [8]. The result of this step is a netlist in Xilinx Netlist Format (XNF) [6]. The circuit in XNF format is simulated using logic simulator ViewSim [8] with the test patterns provided by the designer of the circuit. The XNF netlist is then further processed with the Xilinx software XACT [6] performing technology mapping, in-chip place and route and bitstream configuration for the prototyping design. In the next step, XNF description of the interface controller is automatically generated, based on the final configuration of the design to be implemented in LCA2, PCB netlist of the programmable board and the list of inputs and outputs from the simulation input file. XNF description of the interface controller is then partitioned into LCA1 and LCA3 devices. Both LCA1 and LCA3 XNF netlists are then further processed with XACT to generate configuration bitstreams for both FPGA devices.


Fig. 3: Design flow of the prototyping circuit.

After all LCA's are programmed and the prototyping board is configured, the implemented design can be tested. The assignment of data bit weights of inputs and outputs, and the multiplexing/demultiplexing performed by the control unit is defined from the sequence of inputs and outputs given in the simulation input file. Therefore, we can use the simulation input file with the input signal specification as the initial test vectors, and the results of the functional verification are then directly compared to the simulation results.

Results of the functional verification are illustrated in Fig. 4 for a sample circuit. Results of the software simulation are displayed in a similar form. Comparison of both result files is automated with the functional verification software.


 Editing:   High  Low   SPACE toggle high/low   Insert   Delete 

 ***** Signals: *****                                          
  INSTR0 ____________--------------------------------------
  INSTR1 __________________________________________________
  INSTR2 ____________--------------------------------------
  INSTR3 ____________--------------------------------------
   FLAGV __________________________________________________
   FLAGC __________________________________________________
   FLAGN __________________________________________________
   FLAGZ __------------------------------------------------
   CLOCK ____----____----____----____----____----____----__
   EN_PC ------------________--------________--------------
  INC_PC ____________________--------________--------______
   LD_PC ____--------______________________________________
  LD_MAR ____________--------________--------______________
   LD_IR ____________________--------______________________
   LD_OR ____________________________________--------______
   EN_OR --------------------------------------------------
  LD_MRD __________________________________________________
  LD_ACC __________________________________________________

 Move around with arrows, PgUp/Dn and Home/End !
 F1 Verify   F2 Save   F3 Open   F4 Compare   F5 Auto   F6 Opt

Fig. 4: An example of the functional verification.

IV. Applications of the Prototyping Board

In this section, the sample student projects are described. Most of them are the results of diploma work after 4 years of electrical engineering courses covering digital electronics, CAD and digital signal processing. Some of the typical working designs are described.

The first project deals with the design of the simple 8-bit CPU [9]. This simple, hypothetical CPU is introduced in the first year of electrical engineering study to cover basic operations in computers. It is composed of five 8-bit registers, arithmetic logic unit and 256 bytes of RAM. The registers are: program counter, accumulator, state register, memory address register and memory data register. The CPU is realized within LCA2 and 256 bytes of RAM is addressed at the external memory board. Operation of the CPU as follows: the program, written in the assembly language developed for this CPU, is compiled to the binary instructions and stored in the RAM. The CPU can then operate in two modes, interactive or automatic. In the first mode, the input parameters of the program are interactively inserted by the user via an external I/O card, and the results are displayed on a 7-segment displays. In the automatic mode, all input parameters are stored in the external RAM. Once the program is completed, the results in RAM are transferred to the PC. Rather than simulating the operation of the CPU on the computer with the required software, students can verify their programs in real-time with the programmable hardware.

The traffic controller is a typical student project which illustrates the hierarchy of design, steps of the functional verification and the integration of the real design into the environment. A crossroad of 4 roads including the signals for pedestrians and cyclists is considered [10]. Special attention is paid to the possibility of dominated phase and timing variability of each phase in order to regulate traffic density. The problem of the traffic controller was split into three sub-problems: controller, counter and the control logic to interface both parts. The controller and the counter were described as State Transition Graphs (STGs) and synthesized using SIS [7], while the interface logic was designed on schematic-level using OrCAD [11]. Once the basic traffic controller had been designed, two controllers were cascaded to demonstrate the green phase over two crossroads. The environment, in this case the crossroads with the required traffic lights, is emulated graphically on the PC driven by the signals from the prototyping board. Since we have good experience with these illustrative projects, we are currently working on the similar projects such as washing machine and elevator controllers.

The area of signal processing has been found to be very promising for demonstrating the powerful use of FPGA technology [12]. Since the Xilinx FPGAs exploit the symmetrical array structure, we have automated the design of systolic arrays operating as Finite Impulse Response (FIR) filters [13]. For the required specifications of the filter, the circuit netlist is automatically generated. Final technology mapping, placement and routing is then performed by XACT tool. Due to the regular structure of the systolic arrays, placement and routing in FPGA is relatively simple and it takes only a few minutes on Sun SPARC2 workstation from the initial specification to the working implementation.

The other project considers the adaptive FIR filters based on the Least Mean Square (LMS) algorithm [14]. The goal of the project was to establish the merits for FPGA implementation of these filters. We have experimentally confirmed that the filters, ranging from the first order with 16-bits input word length up to the ninth order with the 4-bit input word length, can be implemented within one XC3195 (LCA2). We have demonstrated noise removal from the speech signal as a typical application of this adaptive FIR filter.

V. Conclusions

In this paper, we have presented a simple prototyping programmable system for very fast implementation of digital electronic circuits. The system is used as a standard tool in the courses covering principles and design of digital circuits. The main advantage of the environment is the simplicity which provides automated implementation and functional verification of the designed circuit. Efficiency for educational purposes has been proven through the various student projects. Based on our current experiences, we are focusing our efforts on designing a modular based hardware prototyping system consisting of multi-FPGA based programmable boards. The new system will keep all the features of the one presented here, as well as providing additional flexibility to implement larger designs.


The authors gratefully acknowledge Mr. Jason Feinsmith, Xilinx University Program for the grant of the XACT software.


[1] G. De Micheli, Synthesis and Optimization of Digital Circuits. McGraw Hill, New York, 1994.

[2] Stephen D. Brown, Robert J. Francis, and Jonathan Rose. Field-Programmable Gate Arrays. Kluwer Academic Publishers, Boston, 1992.

[3] M. Wendling and W. Rosenstiel. A Hardware Environment for Prototyping and Partitioning Based on Multiple FPGAs. In European Design Automation Conference '94, pages 77-82, September 1994.

[4] Zycad. Top 10 Rapid Prototyping Hints.

[5] Xilinx. The Programmable Gate Array Data Book. Xilinx Incorporation, 2100 Logic Drive, San Jose, California, 1995.

[6] Xilinx. User Guide and Tutorials. Xilinx Incorporation, 2100 Logic Drive, San Jose, California, 1995.

[7] SIS - Release 1.2. UC Berkeley Soft. Distr., July 1994.

[8] ViewFPGA. User's Guide, 1994. Viewlogic Systems, Inc.

[9] F. Bratkovic and V. Gustin. Fundamentals of Computers. University Ljubljana Press, Ljubljana, 1995.

[10] B. Zupan, A. Zemva, and B. Zajc. Programmable Integrated Circuit for Traffic Light Controller. In International Symposium on Traffic Electronics, pages 317-322, October 1994.

[11] OrCAD/SDT. User's Guide, 1992. Hillsboro.

[12] L. Mintzer. FIR Filters with Field-Programmable Gate Arrays. Journal of VLSI Signal Processing, 6(2):119-127, August 1993.

[13] H. Froehlich, B. Zajc, and M. Lopez. Implementation of FIR Filters as Systolic Arrays with FPGAs. In Proc. of the Third Electrotechnical and Computer Conference ERK'94, pages 93-96, September 1994.

[14] R. Kranjc. Possible Realizations of Adaptive LMS FIR Filters with FPGAs. In M.Sc. Thesis, University of Ljubljana, July 1995.

Author Contact Information

Andrej Zemva
University of Ljubljana,
Faculty of Electrical Engineering
Trzaska 25
1000 Ljubljana,
Phone: +386 61 1768-346
Fax: +386 61 1264-630

Andrej Trost
University of Ljubljana,
Faculty of Electrical Engineering
Trzaska 25
1000 Ljubljana,
Phone: +386 61 1768-351
Fax: +386 61 1264-630

Baldomir Zajc
University of Ljubljana,
Faculty of Electrical Engineering
Trzaska 25
1000 Ljubljana,
Phone: +386 61 1768-349
Fax: +386 61 1264-630

Author Biographies

Andrej Zemva received his B. Sc., M. Sc. and Ph. D. degrees in electrical engineering from the Faculty of Electrical Engineering, University of Ljubljana in 1989, 1993 and 1996 respectively. His main research interests include computer aided design of integrated circuits, especially logic synthesis and optimization, fault modeling, automatic test pattern generation, hardware emulation and rapid prototyping.

Andrej Trost received his B. Sc. and M. Sc. degrees in electrical engineering from the Faculty of Electrical Engineering, University of Ljubljana in 1995 and 1998. He is the associate researcher at the Faculty of Electrical Engineering, Laboratory for Integrated Circuit Design. His main research interests include rapid prototyping systems, circuit verification and DSP applications in FPGA technology.

Baldomir Zajc received his B. Sc., M. Sc. and Ph. D. degrees in electrical engineering from the Faculty of Electrical Engineering, University of Ljubljana. At this University, he teaches courses covering digital electronics and integrated circuits. His research interests are in the area of computer-aided design with an emphasis on logic synthesis of VLSI circuits and systems. Professor Zajc has been involved in several research projects for telecommunication industry.