N4B2  Circuits for Spectroscopy and Imaging

Thursday, Nov. 5  10:30-12:10  San Diego

Session Chair:  Gianluigi De Geronimo, Brookhaven National Laboratory, United States; Hiroyuki Takahashi, Department of Nuclear Engineering and Management, The University of Tokyo, Japan

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(10:30) N4B2-1, A Readout ASIC for the R3B Silicon Tracker

L. Jones1, S. Bell1, Q. Morrissey1, M. Prydderch1, I. Church1, I. Lazarus2, M. Kogimtzis2, V. Pucknell2, M. Borri2, M. Labiche2, J. Thornhill3

1Technology, STFC Rutherford Appleton Laboratory, Didcot, United Kingdom
2Technology, STFC Daresbury Laboratory, Warrington, United Kingdom
3Physics, University of Liverpool, Liverpool, United Kingdom
A 128 channel event driven ASIC is described which reads out the R3B silicon micro vertex tracker. Ionising particles with energies in the range of 40keV–50MeV are detected, digitised and read out with 12 bit resolution, and time stamped with up to 5ns precision. The ASIC copes with signal charges and detector leakage currents of both polarities and allows charge sharing to be taken into account by reading out the charge from neighbouring channels. The ASIC can recover quickly from signals up to 1Gev, can store up to 32 events and can be easily daisy-chained to reduce parallel connections. Outputs can be Manchester encoded to allow for capacitive coupling of the data, and a 128-bit OR of all the channel hits provides a fast trigger output. Three versions of the ASIC have been manufactured, the third version is currently under test.

(10:50) N4B2-2, Measurement of Ionizing Particles by the PH32 Chip

M. Carna, M. Havranek, Z. Janoska, V. Kafka, M. Marcisovsky, G. Neue, L. Tomasek, V. Vrba

Faculty of Nuclear Sciences and Physical Engineering, Czech Technical University in Prague, Prague, Czech Republic
The PH32 readout chip for measurement of X-rays, beta radiation and ions including alpha particles has been developed recently. The chip was manufactured using a commercial 180 nm CMOS process and can be used in dosimetry, spectroscopy, radiotherapy and medical diagnostics. It is able to measure deposited charge as well as counting hits from a silicon sensor in two operation modes. The first mode is able to measure generated charge in range from 3 ke- to 100 ke- for soft X-rays and beta radiation, the second mode in range from 300 ke- to 10 Me- for alpha particles. The measurement accuracy is about 1500 e- for chip calibration charge of 50 ke- and 180 ke- for calibration charge of 5 Me-. The measurements presented in this paper are focused on the channel response to the injected charge including linearity, gain, channel uniformity, noise and dispersion. Energetic spectrum of 241Am is presented together with the ability to measure dose rate in range of 8-orders of magnitude.

(11:10) N4B2-3, Performance Study of the First 2D Prototype of Vertically Integrated Pattern Recognition Associative Memory (VIPRAM)

N. V. Tran, G. Deptuch, J. Hoff, S. Jindariani, T. T. Liu, J. Olsen

Particle Physics Division, Fermilab, Batavia, IL, USA
Extremely fast pattern recognition capability necessary to find and fit many billions of tracks produced every second anticipated at high luminosity LHC (HL-LHC) running conditions. Associative Memory (AM) based approach was proposed as potential solution to the tracking trigger. However, the number of patterns required to perform charged track pattern recognition at HL-LHC is much larger than what has been used previously. The Vertically Integrated Pattern Recognition Associative Memory (VIPRAM) Project aims to achieve the target pattern density and performance goal using 3DIC technology with through-silicon vias (TSVs). The first step taken in the VIPRAM work was the development of a 2D prototype (protoVIPRAM00) in which the associative memory building blocks were designed to be compatible with the 3D integration. This means that the building blocks were laid out as if this was a 3D design, but room was left for as yet non-existent TSVs and routing was performed to avoid these areas. Detailed description of the chip design, timing studies based on Corner and Monte Carlo analysis, and the initial testing results of the protoVIPRAM has been reported last year at TWEPP workshop. In this paper, we will present the results from extensive performance studies of the protoVIPRAM00 chip in both pseudo-realistic HL-LHC and stress conditions. Results indicate that the chip operates at the design frequency with 100% correctness in pattern recognition. We also present performance boundary characterization of the chip and conclude that the building blocks are ready for 3D stacking.

(11:30) N4B2-4, UFCX32k – Ultra Fast Single Photon Counting Chip with Energy Window for Hybrid Pixel Detector

P. Grybos, P. Kmon, P. Maj, R. Szczygiel

Measurement and Electronics, AGH University of Science and Technology, Krakow, Poland
The UFXC32k integrated circuit designed in CMOS 130 nm process, contains about 50 million transistors in the area of 9.64 mm x 20.15 mm. The core of the IC is the matrix of 128 x 256 square shaped pixels of 75 µm pitch. Each pixel contains a charge sensitive amplifier, a shaper, a discriminator, correction circuits and two 14-bit counters. The data is read out via 8 Low Voltage Differential Signaling (LVDS) outputs. The UFXC32k chip is bump-bonded to a pixel silicon sensor and fully characterized in X-ray radiation. The measured equivalent noise charge is equal to 123 e- rms (for the peaking time of 40 ns) and each pixel dissipates 26 µW. Thanks to the use of multilevel offset correction, an effective offset spread calculated to the input is only 9 e- rms with the gain spread of 2 %. The count rate per pixel depends of the effective CSA feedback resistance and in the fast mode a dead time of the front-end electronics is about 100 ns (paralyzable model).

(11:50) N4B2-5, A Low-Power Low-Noise Synchronous Pixel Front-End Chain in 65 nm CMOS Technology with Local Fast ToT Encoding and Autozeroing for Extreme Rate and Radiation at HL-LHC

L. Pacher1,2, E. Monteil1,2, A. Rivetti2, N. Demaria2, M. D. Da Rocha Rolo2

1Department of Physics, University of Torino, Torino, Italy
2Section of Torino, Istituto Nazionale di Fisica Nucleare (INFN), Torino, Italy
A low-power and low-noise synchronous front-end chain in a commercial 65 nm CMOS technology suitable for the future pixel upgrades at the CERN Large Hadron Collider (LHC) is presented. A shaper-less charge-sensitive amplifier with constant current feedback provides triangular pulse shaping for linear time-over-threshold (ToT) charge measurements. Sensor leakage currents are compensated by the same feedback network. A track-and-latch voltage comparator is proposed for the hit discrimination. The hit generation is synchronized with a 40 MHz clock, avoiding time-walk issues in the time-stamp assignment. Fast ToT charge encoding up to 8-bit resolutions can be retrieved at the pixel level using high-frequency self-generated clock signals obtained by turning the latch into a voltage-controlled oscillator using asynchronous logic. Pixel-to-pixel threshold variations are compensated by means of an autozeroed scheme, without the usage of a on-pixel D/A converter. A pixel array of 8 × 8 pixel cells with 50 µm × 50 µm pixel size has been prototyped. Design specifications, implementation and test results will be discussed.