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Technical Seminar

From I-25, take Harmony Road Exit (Exit 265) westbound, and enter AMD campus on right immediately following Harmony/Ziegler intersection.  AMD is located on the NW corner of Harmony Road and Ziegler Road.  Proceed to 3rd floor for escort to seminar auditorium.  Non-AMD employees:  please arrive at 4:15pm for security sign-in and escort.

Modern high-performance computing and networking system designs are pushing data
rates for inter-chip communications to unprecedented speeds.  Both on-board buses such
as CPU-Memory and CPU-Coprocessor and backplane buses in blade systems, storage,
and networking gear are being increased in data rate to a range of 5 to 10Gb/s in modern system designs.  These high data rates require the design of advanced equalization I/O cores which are capable of operating in the challenging high frequency channel with higher loss, higher crosstalk, and more reflection distortion compared to lower data rate systems.  This talk will cover highlights from a study of equalization performance on 10Gb/s IEEE 802.3ap backplanes presented by the author at the 2006 ISSCC ATAC.  Topics covered include an overview of the challenges presented by the electrical interconnect  channel at high data rates, including channel characteristics of a range of informative backplanes  presented to the IEEE 802.3ap "Ethernet over Backplane" standard.   Both transmitter and receiver  (typically FFE and DFE) equalization will be compared and contrasted.  The system level
architecture  and performance of a modern 10Gb/s I/O core which realizes FFE and DFE equalization will be discussed.  An overview of behavioral link simulation will be presented, illustrating components of a typical link simulation tool along with important I/O core parameters which need to be modeled to accurately predict system performance.  Example simulation results which summarize expected performance as a function of various system design parameters such as FFE and DFE length and I/O core degradations are given with a focus on the IEEE 802.3ap application channels.  Conclusions are drawn summarizing major challenges facing modern high data rate I/O system designs.

• IEEE 802.3ap Backplane Ethernet Task Force
  • Channel Modeling
• J. Bulzacchelli et al., "A 10-Gb/s 5_Tap DFE/4-Tap FFE Transceiver in 90-nm CMOS Technology," IEEE J. Solid-State Circuits, vol. 41, no. 12, Dec. 2006 (copyright by IEEE)
• M. Meghelli et al., "A 10Gb/s 5-Tap-DFE/4-Tap-FFE Transceiver in 90nm CMOS," ISSCC 2006 (copyright by IEEE)
• T. Beukema et al., "A 6.4Gb/s CMOS SerDes Core with Feed-forward and Decision-Feedback Equalization," IEEE J. Solid-State Circuits, vol. 40, no. 12, Dec. 2005 (copyright by IEEE)
• M. Sorna et al., "A 6.4Gb/s CMOS SerDes Core with Feedforward and Decision-Feedback Equalization," ISSCC 2005 (copyright by IEEE)

As part of this effort, he works closely with both IBM ASIC development groups and colleagues in research at Yorktown in the design of receiver analog front end architecture, clock-and-data recovery algorithms, and equalization adaptation algorithms.  He has written a fast behavioral serial link simulator which is in use at IBM research and product development groups to both assist in the development of advanced I/O core architectures and provide a tool to system level designers for analysis of end-to-end serial link performance for a wide range of high speed I/O applications.