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Technical Forum
Intel Itanium Processor (Montecito)
DATE/TIME Thursday, March 31, 2005 (4:30pm to 6:30pm)
PLACE  Bldg. 1 Auditorium (Agilent Technologies, Fort Collins, CO)
Non-Agilent/HP/Intel Attendees:  Please arrive punctually at 4:15pm as you will need to be escorted to the seminar room.  We appreciate a courtesy RSVP to bob_barnes@agilent.com to expedite sign-in and to help us with a headcount estimate for food/drinks.
DIRECTIONS

From I-25, take Harmony Road Exit (Exit 265) westbound, and enter Agilent/HP campus on right.  Agilent/HP campus is on the NE corner of Harmony Road and Ziegler Road.  Proceed to Bldg. 1 Lobby to sign-in and meet host for escort to Auditorium.
COST    Free.  As always, pizza & drinks will be provided.
ABSTRACT
This special forum is an encore presentation of the four Itanium microprocessor papers presented last month at ISSCC (International Solid-State Circuits Conference) in San Francisco, CA.
Seminar 1:  The Implementation of a 2-core Multi-Threaded Itanium-Family Processor
  • The next generation in the Itanium family processor family, code-named Montecito, is introduced.  Implementation in a 90nm 7M process, the processor has two dual-threaded cores integrated with 26.5MB of cache.  Of the total of 1.72B transistors, 64M are dedicated to logic and the rest to cache.  With both cores operating at full speed, the chip consumes 100W.
  • Authors: Sam Naffziger, Blaine Stackhouse, Tom Grutkowski
  • Speaker: Sam Naffziger (biography)
  • ISSCC Paper Presentation Slides (copyright by IEEE)
Seminar 2:  Clock Distribution on a Dual-Core Multi-Threaded Itanium-Family Processor
  • Clock distribution on the 90nm Itanium processor is detailed.  A region-based active de-skew system reduces the PVT sources of skew across the entire die during normal operation.  Clock vernier devices inserted at each local clock buffer allow up to a 10% clock-cycle adjustment via firmware or scan.  The system supports a constantly varying frequency and consumes <25W from PLL to latch while providing <10ps of skew across PVT.
  • Authors: Patrick Mahoney, Eric Fetzer, Bruce Doyle, Sam Naffziger
  • Speaker: Patrick Mahoney (biography) Bruce Doyle (biography)
  • ISSCC Paper Presentation Slides (copyright by IEEE)
Seminar 3:  A 90nm Variable-Frequency Clock System for a Power-Managed Itanium-Family Processor
  • A clock-generation system delivers fixed- and variable-frequency clocks for adaptive power control on a 1.7B-transistor dual-core CPU.  Frequency synthesizers digitally divide a fixed-frequency PLL clock in 1/64th cycle steps using programmable voltage-frequency-converter loops.  1-cycle loop response tracks supply transients with adaptive modulation, improving CPU performance by over 10% compared to a fixed-frequency design.
  • Authors: Tim Fischer, Ferd Anderson, Ben Patella, Sam Naffziger
  • Speaker: Ben Patella (biography)
  • ISSCC Paper Presentation Slides (copyright by IEEE)
Seminar 4:  Power and Temperature Control on a 90nm Itanium-Family Processor
  • This paper describes the embedded feedback and control system on a 90nm Itanium-family processor, code-named Montecito, that maximizes performance while staying within a target power and temperature (PT) envelope.  This system utilizes on-chip sensors and an embedded micro-controller to measure PT and modulate voltage and frequency to meet PT constraints.
  • Authors: Christopher Poirier, Richard McGowen, Christopher Bostak, Sam Naffziger
  • Speaker: Jim Ignowski (biography)
  • ISSCC Paper Presentation Slides (copyright by IEEE)

SAM NAFFZIGER (Intel, Fort Collins, CO)
Sam Naffziger is an Intel fellow directing Itanium Circuits and Technology in the Digital Enterprise Group. He provides technical direction for the design of Itanium microprocessors and exploring and developing technologies for a broad range of Intel's server processors.  Naffziger joined Intel in 2005 as part of Intel's hiring action of the Hewlett-Packard processor design team, in which he led development of the Itanium2 processor roadmap for eight years.  He joined HP in 1988 in the ASIC design group before moving to processor development where he became a technical lead for PA-RISC processor development and contributed to significant advances in that architecture.  He holds 59 U.S. patents and has published papers in the Journal of Solid-State Circuits and the Journal of VLSI.
PATRICK MAHONEY (Intel, Fort Collins, CO)
Patrick Mahoney is a Staff Engineer at Intel and works on the Itanium family of processors in the Digital Enterprise Group where his focus has been on high-speed digital circuit design.  He joined Intel in 1995 and worked on the cache design of Intel's Pentium microprocessor.  In 1997, he moved to Fort Collins, CO, and joined the Itanium 2 microprocessor team working on circuitry for the L1 data cache for the first Itanium 2 codenamed McKinley.  More recently he worked on the design of the clock distribution system on the newest Itanium processor code named Montecito.  He holds a BSc and MSc Electronics from Durham University, Durham, United Kingdom.
BRUCE DOYLE (Intel, Fort Collins, CO)
Bruce Doyle is a Staff Engineer at Intel and works on the Itanium family of processors in the Digital Enterprise Group.  His main focus has been circuit and architectural contributions to the advance clocking system found the newest Itanium processor code named Montecito.  Doyle joined Intel in 2005 as part of Intel's hiring action of the Hewlett-Packard processor design team.  He joined HP in 2002 and since then has focused on the design and development of high speed links based I/Os and advanced clocking systems.  Prior to joining HP he worked in the areas of memories, graphic accelerators, and LCOS displays with a strong focus on mixed signal and analog design.  He holds 11 U.S. Patents.
BEN PATELLA (Intel, Fort Collins, CO)
Ben Patella is a Design Engineer at Intel and works on the Itanium family of processors in the Digital Enterprise Group.  His main focus has been circuit and architectural contributions to Montecito's Voltage to Frequency Converter, which enables variable frequency clocks for Foxton power management.  Patella joined Intel in 2005 as part of Intel's hiring action of the Hewlett-Packard processor design team.  He joined HP in 2001 after receiving his BS in Computer Engineering and MSEE from the University of Colorado, Boulder, CO.  Patella's M.S. thesis, "Implementation of a Low-Power, High Frequency Digital Pulse Width Modulation Controller", won the Engineering College award for Excellence in Scholarship and Research.
JIM IGNOWSKI (Intel, Fort Collins, CO)
Jim Ignowski is currently employed by Intel, working on the Itanium family of processors in the Digital Enterprise Group.  His primary focus is analog circuit design for thermal and power management (Foxton Technology) on the newest Itanium processor code named Montecito.  Ignowski joined Intel in 2005 as part of Intel's hiring action of the Hewlett-Packard processor design team.  He joined HP in 1984 and held a number of individual contributor and technical management positions in R&D, manufacturing, and marketing.  He has a BSEE from Rice University, Houston, TX, and an MSEE from Stanford University, Stanford, CA, and holds 3 U.S. Patents.
PHOTOS  Courtesy of Bob Barnes