Advance Program

 Advance Program (As of March 12, 2018) PDF (62KB)

Wednesday, March 14

Main Hall (Shinsho-Hall A+B)

8:30-9:00 Opening

Opening Remarks, Hitoshi Wakabayashi, General Chair of EDTM 2018, Tokyo Institute of Technology

9:00-11:00 Plenary Session

Kazunari Ishimaru, Toshiba Memory Corp.
PL-1   9:00-9:40

Logic Technology Scaling to Continue Moore's Law, Mark T. Bohr, Intel Corporation

PL-2   9:40-10:20

2D Materials for Smart Life, Kaustav Banerjee, University of California, Santa Barbara

PL-3   10:20-11:00

Evolution of the GPU Device Widely Used in AI and Massive Parallel Processing, Toru Baji, NVIDIA (Japan)

11:00-11:45 Exhibition Talks

Hisataka Hayashi, Toshiba Memory Corp.
Coventor, A Lam Research Company
Toshiba Memory Corporation
Atomera Inc.
MKS Japan, Inc.
National Institute of Advanced Industrial Science and Technology (AIST)
tei Solutions Inc.

13:15-14:30 Session 3M - Device: Super Steep Slope Devices 1

Kejun Xia, NXP Semiconductors
3M-1   13:15-13:40

Design Considerations of Ferroelectric Properties for Negative Capacitance MOSFETs, Ali Saeidi, Farzan Jazaeri, Igor Stolichnov, Christian C. Enz, and Adrian M. Ionescu, Ecole Polytechnique Fédérale de Lausanne

3M-2   13:40-14:05

Analysis of Negative Capacitance UTB SOI MOSFETs Considering Line-Edge Roughness and Work Function Variation, Pin-Chieh Chiu and Vita Pi-Ho Hu, National Central University

3M-3   14:05-14:30

Investigation of Fin-Width Sensitivity of Threshold Voltage for InGaAs/Si Channel Negative-Capacitance FinFETs, Shih-En Huang and Pin Su, National Chiao Tung University

14:55-15:30 Authors Interview

Room C (Conference Room 3)

13:15-14:55 Session 3C - Material: 2D Related Materials

Iriya Muneta, Tokyo Tech.
Paul Berger, Ohio State Univ.
3C-1   13:15-13:40 (Invited)

2D Materials for Ubiquitous Electronics, Saptarshi Das, Pennsylvania State University

3C-2   13:40-14:05

Synthesis and Characterization of Novel TMD: Rhenium Disulfide, Michael D. Valentin1,2, Alison Guan1, Ariana E. Nguyen1, I-Hsi Lu1, Cindy S. Merida1, Michael J. Gomez1, Madan Dubey2, and Ludwig Bartels1, 1University of California, 2U.S. Army Research Laboratory

3C-3   14:05-14:30 (Invited)

3D Foams as a New Thermal Material for a Variety of Applications, Hang Tong Edwin Teo, Nanyang Technological University

3C-4   14:30-14:55

Anisotropic Thermal Conductivity of Vertically Self-Ordered Nanocrystalline Boron Nitride Thin Films for Thermal Hotspot Mitigation in Electronics, Siu Hon Tsang1, Olivier Cometto2, Majid Kabiri Samani3, Shuangxi Sun3, Johan Liu3, and Edwin Hang Tong Teo1, 1Nanyang Technological University, 2CINTRA CNRS/NTU/THALES, 3Chalmers University of Technology

14:55-15:30 Authors Interview

Room D (Barcelona)

13:15-14:55 Session 3D - Modeling & Reliability: Modeling for Reliability

Lining Zhang, Shenzhen Univ.
Xianping Chen, Chongqing Univ.
3D-1   13:15-13:40 (Invited)

Modeling of Carrier Trapping and Its Impact on Switching Performance, Mitiko Miura-Mattausch, Hideyuki Kikuchihara, Dondee Navarro, and Hans Jürgen Mattausch, Hiroshima University

3D-2   13:40-14:05

Consistent Predictive Simulation of SRAM-Cell Performance Degradation Including Both MOSFET Fabrication Variation and Aging, Hiroaki Gau1, Nezam Rohbani2, Tapas K. Maiti1, Dondee Navarro1, Mitiko Miura-Mattausch1, Hans Jürgen Mattausch1, and Hirotaka Takatsuka3, 1Hiroshima University, 2Sharif University of Technology, 3Mie Fujitsu Semiconductor Limited

3D-3   14:05-14:30

Non-Universal Temperature Dependence of Hot Carrier Degradation (HCD) in FinFET: New Observations and Physical Understandings, Zhuoqing Yu1, Runsheng Wang1, Peng Hao2, Shaofeng Guo1, Pengpeng Ren1, and Ru Huang1, 1Peking University, 2now at University of California, Irvine

3D-4   14:30-14:55

Comprehensive 3D TSV Reliability Study on 14nm FINFET Technology with Thinned Wafers, C. S. Premachandran, Salvatore Cimino, Sean Ogdan, Zhuo-Jie (George) Wu, Daniel Smith, and Sukesh Kannan, Linjun Cao, Manjunatha Prabhu, Walter Yao, Rakesh Ranjan, Luke England, and Patrick Justison, GLOBALFOUNDRIES Inc.

14:55-15:30 Authors Interview

14:55-15:30 Poster Viewing in Event Hall

*For Poster Session, please see the detailed information. (click here)

Room C (Conference Room 3)

15:30-16:45 Session 4C - Process: Dry Etching and Ion Implantation

Kazuo Nojiri, Lam Research
Yoji Kawasaki, Sumitomo Heavy Industries Ion Technology Co., Ltd.
4C-1   15:30-15:55 (Invited)

Atomic Layer Etching: Benefits and Challenges, Thorsten Lill, Keren J. Kanarik, Samantha Tan, Skip Berry, Andreas Fischer, Vahid Vahedi, and Richard A. Gottscho, Lam Research

4C-2   15:55-16:20


4C-3   16:20-16:45

Ion Implantation Synthesis of Si-Doped HfO2 Ferroelectric Thin Films, Shinji Migita1, Hiroyuki Ota1, Hiroyuki Yamada1, Keisuke Shibuya1, Akihito Sawa1, Takashi Matsukawa1, and Akira Toriumi2, 1National Institute of Advanced Industrial Science and Technology (AIST), 2The University of Tokyo

16:45-17:00 Authors Interview

Room D (Barcelona)

15:30-16:45 Session 4D - Device: Advanced CMOS

Naoto Horiguchi, IMEC
Gong Xiao, National Univ. of Singapore
4D-1   15:30-15:55

Potential Influence of Surface Atomic Disorder on Fermi-Level Pinning at Metal/SiGe Interface, X. Luo, T. Nishimura, T. Yajima, and A. Toriumi, The University of Tokyo

4D-2   15:55-16:20

Enhanced Germanium-Tin P-Channel FinFET Performance Using Post-Metal Anneal, Dian Lei1, Kwang Hong Lee2, Yi-Chiau Huang3, Shuyu Bao2,4, Wei Wang1, Saeid Masudy-Panah1, Sachin Yadav1, Annie Kumar1, Yuan Dong1, Yuye Kang1, Shengqiang Xu1, Ying Wu1, Chuan Seng Tan2,4, Xiao Gong1, and Yee-Chia Yeo1,5, 1National University of Singapore, 2SMART, 3Applied Materials, 4Nanyang Technological University, 5Currently with TSMC

4D-3   16:20-16:45

Polarity Control in WSe2 Field-Effect Transistors Using Dual Gate Architecture, Hiroyuki Takagi, Ryo Ikoma, Tomoaki Oba, and Takamasa Kawanago, Tokyo Institute of Technology

16:45-17:00 Authors Interview

16:45-18:00 Poster Viewing in Event Hall

*For Poster Session, please see the detailed information. (click here)

Thursday, March 15

Room A (Shinsho-Hall A)

8:30-9:45 Session 5A - Featuring: Artificial Intelligence and Enabling Devices 1

Kazunari Ishimaru, Toshiba Memory Corp.
Carlo Reita, CEA-LETI
5A-1   8:30-8:55 (Invited)

Steep Slope Transistors for Quantum Computing, Adrian M. Ionescu, Teodor Rosca, and Cem Alper, Ecole Polytechnique Fédérale de Lausanne

5A-2   8:55-9:20

Energy and Area Efficient Tunnel FET-Based Spiking Neural Networks, Dinesh Rajasekharan1, Sarvesh S. Chauhan1, Amit Ranjan Trivedi2, and Yogesh Singh Chauhan1, 1Indian Institute of Technology, Kanpur, 2University of Illinois at Chicago

5A-3   9:20-9:45

Electrode Material Dependence of Resistive Switching Behavior in Ta2O5 Resistive Analog Neuromorphic Device, Hisashi Shima, Makoto Takahashi, Yasuhisa Naitoh, and Hiroyuki Akinaga, National Institute of Advanced Industrial Science and Technology (AIST)

9:45-10:40 Authors Interview

Room B (Shinsho-Hall B)

8:30-10:10 Session 5B - Package: Photonics Related Technologies

Eric Beyne, IMEC
Yoichiro Kurita, Toshiba Corp.
5B-1   8:30-8:55 (Invited)

An Advanced CuCu Hybrid Bonding for Novel Stacked CMOS Image Sensor, Y. Kagawa1, N. Fujii2, K. Aoyagi2, Y. Kobayashi1, S. Nishi1, N. Todaka1, S. Takeshita1, J. Taura1, H. Takahashi2, Y. Nishimura2, K. Tatani2, M. Kawamura1, H. Nakayama1, K. Ohno2, H. Iwamoto2, S. Kadomura1, and T. Hirayama2, 1Sony Semiconductor Manufacturing, 2Sony Semiconductor Solutions

5B-2   8:55-9:20

Interfacial Failure Characterization of Electronic Packaging Component Using a Multiscale Modelling Approach, Zhen Cui1,2, Yingying Zhang1, Qun Yang1, Guoqi Zhang2, and Xianping Chen1,2, 1Chongqing University, 2Delft University of Technology

5B-3   9:20-9:45

Heterogeneous Integration of GaN LED on CMOS Driver Circuit for Mobile Phone Applications, S. Lawrence Selvaraj1, Lulu Peng1, Zou Qiong2, Yeo Kiat Seng2, and Don Disney1, 1GLOBALFOUNDRIES Inc., 2Singapore University of Technology and Design (SUTD)

5B-4   9:45-10:10 (Invited)

Silicon Photonic Multiport Optical Switch and Its Control Electronics, Hitoshi Kawashima, Ken Tanizawa, Keijiro Suzuki, Hiroyuki Matsuura, Satoshi Suda, Guangwei Cong, Ryotaro Konoike, Shu Namiki, and Kazuhiro Ikeda, National Institute of Advanced Industrial Science and Technology (AIST)

10:10-10:40 Authors Interview

Room C (Conference Room 3)

8:30-10:10 Session 5C - Modeling & Reliability: Device Modeling

Dondee Navarro, Hiroshima Univ.
5C-1   8:30-8:55

Ballistic Mobility Model for QDD Simulation of Ultra-Short Transistors, P. Aguirre and A. Schenk, Integrated Systems Laboratory

5C-2   8:55-9:20

Study on the Direct Relationship between Macroscopic Electrical Parameters and Microscopic Channel Percolative Properties in Nanoscale MOSFETs, Zhe Zhang, Runsheng Wang, Shaofeng Guo, Yangyuan Wang, and Ru Huang, Peking University

5C-3   9:20-9:45 (Invited)

Thin-Film Transistor Compact Model and AMOLED Applications, Di Geng, Jin Chen Cao, Yue Su, Ling Li, and Ming Liu, Chinese Academy of Sciences

5C-4   9:45-10:10

A Smooth and Continuous Phase Change Memory SPICE Model for Improved Convergence, Dayong Liu1, Lining Zhang2, Xinnan Lin1, and Mansun Chan2, 1Peking University, 2Hong Kong University of Science and Technology

10:10-10:40 Authors Interview

Room D (Barcelona)

8:30-10:10 Session 5D - Yield & Manufacturing: DFM and Product Yield

Angelo Pinto, Qualcomm
Bill Nehrer, Consultant
5D-1   8:30-8:55 (Invited)

Design and Technology Co-Optimization for exploring Power, Performance, Area and Manufacturability Trade-offs in Advanced FDSOI and FinFET Technologies, Mahbub Rashed, Shibly Ahmed, Navneet Jain, Juhan Kim, Sushama Davar, Pala Balasubramaniam, James Blatchford, and Ravi Todi, GLOBALFOUNDRIES Inc.

5D-2   8:55-9:20

Low Cost and Highly Manufacturable MOL/BEOL Constructs in 22FDSOI Technology for High Performance and Low Power Applications, Navneet Jain1, Juhan Kim1, Sushama Davar1, Shibly Ahmed1, Jeff Kim1, Arif Siddiqi1, Thomas Herrmann1, Joerg winkler1, Frank Barth1, Jens Pika1, Michael Zier1, Jamie Schaeffer1, Mahbub Rashed1, Anurag Mittal1, James Blatchford1, Sunil Machha2, Siva Krisha Potta2, Atul Kumar Kashyap2, Sravan Kumar Tekuru2, Bipin Malahan2, and Ram Prasad Gopannagari2, 1GLOBALFOUNDRIES Inc., 2Invecas Inc.

5D-3   9:20-9:45 (Invited)

Pre-Tapeout Design for Yield Application: Design Based Diffing, Pattern Analytics and Risk Scoring, Rami Salem1, Vic Vadi1, Angelo Pinto1, Piyush Pathak2, Ya-Chieh Lai2, Frank Gennari2, and Philippe Hurat2, 1Qualcomm Technologies, Inc., 2Cadence Design Systems, Inc.

5D-4   9:45-10:10

Process Cost and Time in Minimal Fab to Fabricate Custom-Made Microneedle Array with Extraction Tool, Sommawan Khumpuang1,2, Hiroyuki Tanaka1,2, Norio Umeyama1,2, and Shiro Hara1,2, 1National Institute of Advanced Industrial Science and Technology (AIST), 2Minimal Fab General Incorporated Association

10:10-10:40 Authors Interview

Room A (Shinsho-Hall A)

10:40-12:20 Session 6A - Process: Advanced Thin Film Technology

Yasutoshi Okuno, TSMC
Makoto Miura, Hitachi High-Technologies Corp.
6A-1   10:40-11:05 (Invited)

Thin Film Process Technologies for Continued Scaling, Robert Clark, Tapily Kanda, Kai-Hung Yu, Takahiro Hakamata, Steve Consiglio, David O'Meara, Cory Wajda, Jeffrey Smith, and Gert Leusink, TEL Technology Center, America, LLC

6A-2   11:05-11:30 (Invited)

Technology Innovations in Selective ALD for Next-Generation Contacts and Vias, Suman Datta1 and Andrew Kummel2, 1University of Notre Dame, 2University of California, San Diego

6A-3   11:30-11:55

Chip-Level-Integrated nMISFETs with Sputter-Deposited-MoS2 Thin Channel Passivated by Al2O3 Film and TiN Top Gate, Kentaro Matsuura1, Jun'ichi Shimizu1, Mayato Toyama1, Takumi Ohashi1, Iriya Muneta1, Seiya Ishihara2, Kuniyuki Kakushima1, Kazuo Tsutsui1, Atsushi Ogura2, and Hitoshi Wakabayashi1, 1Tokyo Institute of Technology, 2Meiji University

6A-4   11:55-12:20

Strategies for Growing Perovskite Films on Nanostructured TiO2 for High Performance Solar Cell, Changwen Liu1, Annie Ng1, Zhiwei Ren1, Patrick W. K. Fong1, Gang Li1, and Charles Surya1,2, 1The Hong Kong Polytechnic University, 2Nazarbayev University

12:20-13:50 Authors Interview

Room B (Shinsho-Hall B)

10:40-12:20 Session 6B - Material: Oxide Materials

Hiroyasu Yamahara, The Univ. of Tokyo
Pei-Wen Li, National Chiao Tung Univ.
6B-1   10:40-11:05 (Invited)

Functional Oxide Engineering for Solar Energy Harvesting and Neuromorphic Devices Based on Spintronics & Magnonics, Hitoshi Tabata, Hiroyasu Yamahara, Munetoshi Seki, Akihiro Katogi, Ryota Kikuchi, and Hideto Sato, The University of Tokyo

6B-2   11:05-11:30

Superparamagnetic, Nanocrystalline Cobalt Nickel Zinc Ferrite Thin Films, Deposited at Sub-200℃ for RF CMOS Applications, Neelima Sangeneni, Navakanta Bhat, and S. A. Shivashankar, IISc

6B-3   11:30-11:55

Nucleation-Driven Ferroelectric Phase Formation in ZrO2 Thin Films – What Is Different in ZrO2 from HfO2 ?–, Shigehisa Shibayama1, Tomonori Nishimura1, Shinji Migita2, and Akira Toriumi1, 1The University of Tokyo, 2Nati

6B-4   11:55-12:20

Direct Observation of Chemical States in ReRAM by Laser-Based Photoemission Electron Microscopy, Toshiyuki Taniuchi1,2, Junpei Kawakita1,2, Hisashi Shima2, Yasuhisa Naito2, Hiro Akinaga2, and Shik Shin1,2, 1The University of Tokyo, 2National Institute of Advanced Industrial Science and Technology (AIST)

12:20-13:50 Authors Interview

Room C (Conference Room 3)

10:40-12:20 Session 6C - Device: 3D and MEMS

Osbert Cheng, UMC
Ken Uchida, Keio Univ.
6C-1   10:40-11:05

Impact of 1μm TSV Via-Last Integration on Electrical Performance of Advanced FinFET Devices, Gaspard Hiblot, Stefaan Van Huylenbroeck, Geert Van der Plas, Bart De Wachter, Adrian Vaisman Chasin, Ben Kaczer, Thomas Chiarella, Jerome Mitard, Steven De Muynck, Gerald Beyer, and Eric Beyne, IMEC

6C-2   11:05-11:30 (Invited)

Monolithic 3D (M3D) Complementary Metal-Oxide-Semiconductor (CMOS)-Nanoelectromechanical (NEM) Hybrid Circuits, Woo Young Choi, Sogang University

6C-3   11:30-11:55

Design Optimization Study of Reconfigurable Interconnects, Urmita Sikder1, Giulia Usai2, Louis Hutin2, and Tsu-Jae King Liu1, 1University of California, Berkeley, 2CEA Leti Minatec Campus

6C-4   11:55-12:20

Fabrication and Characterization of Fully Depleted SOI MOSFETs on Ultrathin Circular Diaphragms Using Cost-Effective Minimal- Fab Process, Y. X. Liu1, H. Tanaka1, N. Umeyama1,2, K. Koga1, S. Khumpuang1,2, M. Nagao1, T. Matsukawa1, and S. Hara1,2, 1National Institute of Advanced Industrial Science and Technology (AIST), 2Minimal Fab General Incorporated Association

12:20-13:50 Authors Interview

Room D (Barcelona)

10:40-11:55 Session 6D - Featuring: Heterogeneous Integration

Kamal Shikka, IBM
6D-1   10:40-11:05

Fan-out Wafer-Level Technology – A New Trajectory for Moore's Law Scaling, Rajendra D. Pendse, Qualcomm

6D-2   11:05-11:30

Heterogeneous Integration Using the Silicon Interconnect Fabric, Subramanian S. Iyer, University of California, Los Angeles

6D-3   11:30-11:55 (Invited)

High-Density Fan-Out Technology for Advanced SiP and Heterogeneous Integration , WonChul Do, Amkor Technology Korea

11:55-13:50 Authors Interview

13:30-14:30 Poster Viewing / Exhibition in Event Hall

*For Poster Session, please see the detailed information. (click here)

Room A (Shinsho-Hall A)

14:30-16:10 Session 7A - Modeling & Reliability: Reliability

Mahadeva Iyer Natarajan, Univ. of California, Los Angeles
7A-1   14:30-14:55 (Invited)

Soft Error Rate from Planar to FinFETs On Bulk Vs SOI Processes , Krishna Mohan Chavali and Mahadeva Iyer Natarajan, GLOBALFOUNDRIES Inc.

7A-2   14:55-15:20

Defect Spectroscopy from Electrical Measurements: A Simulation Based Technique, Luca Larcher1, Andrea Padovani2, Dipankar Pramanik2, Ben Kaczer3, and Felix Palumbo4, 1University of Modena and Reggio Emilia, 2MDLSoft Inc., 3IMEC, 4National Technological University

7A-3   15:20-15:45

by the Self-Heating Effect in 14nm High-K Metal-Gate FinFET, E. R. Hsieh1, M. J. Jiang1, H. W. Chen1, J. L. Lin1, Steve S. Chung1, T. P. Chen2, Y. H. Yeah2, T. J. Chen2, and Osbert Cheng2, 1National Chiao Tung University, 2United Microelectronics Corporation (UMC)

7A-4   15:20-15:45

Understanding the Impact of High-K Post Deposition Anneal Temperature on FinFET Reliability – Trade-Offs, Optimization and Mitigation, P. Srinivasan, R. Ranjan, S. Cimino, B. Kannan, and M. Zhu, GLOBALFOUNDRIES Inc.

16:10-16:30 Authors Interview

Room B (Shinsho-Hall B)

14:30-15:45 Session 7B - Featuring: Artificial Intelligence and Enabling Devices 2

Kazunari Ishimaru, Toshiba Memory Corp.
Naoto Horiguchi, IMEC
7B-1   14:30-14:55

Deep Neural Network for Device Modeling, Yuan Lei, Xiao Huo, and Beiping Yan, Hong Kong Applied Science and Technology Research Institute Company Limited

7B-2   14:55-15:20

A Two-Terminal Electric-Double-Layer Synaptic Device with Short- Term Plasticity, Jiabin Wang, Yuxing Li, Ying Zhang, He Tian, Renrong Liang, Yi Yang, and Tian-Ling Ren, Tsinghua University

7B-3   15:20-15:45

Emulating the Short-Term Plasticity and Filtering of Biological Synapses with IZO-Based Electric-Double-Layer Transistors, Xiang Wan1,2, Fei Gao1, Xiaojuan Lian1, Zheng Shi1, Xiao Gong3, Yufeng Guo1, and Yi Tong1,4, 1Nanjing University of Posts and Telecommunications, 2Nanjing University, 3National University of Singapore, 4University of California, Santa Barbara

15:45-16:30 Authors Interview

Room C (Conference Room 3)

14:30-15:45 Session 7C - Material: Advanced Material Processes

Gil Nonato Santos, De La Salle Univ.
Ng Geok Ing, Nanyang Technological Univ.
7C-1   14:30-14:55

Suppressing Oxidation-Enhanced Diffusion of Boron via Buried Epitaxial Oxygen-Inserted Layers in Silicon, Daniel Connelly1, Richard Burton1, Nyles W. Cody1, Pavel Fastenko2, Marek Hytha1, Robert Stephenson1, Hideki Takeuchi1, and Robert Mears1, 1Atomera, Inc., 2Synopsys, Inc.

7C-2   14:55-15:20

Gettering Mechanism in Carbon-Cluster-Ion-Implanted Epitaxial Silicon Wafers Using Atom Probe Tomography, Ayumi Onaka- Masada1,2, Ryosuke Okuyama2, Satoshi Shigematsu2, Hidehiko Okuda2, Takeshi Kadono2, Ryo Hirose2, Yoshihiro Koga2, Koji Sueoka1, and Kazunari Kurita2, 1Okayama Prefectural University, Okayama, Japan, 2SUMCO Corporation

7C-4   15:20-15:45(Invited)

New Contact Metallization Scheme for FinFET and Beyond, Junichi Koike, Maryamsadat Hosseini, Daisuke Ando, and Yuji Sutou, Tohoku University

15:45-16:30 Authors Interview

Room D (Barcelona)

14:30-16:10 Session 7D - Device: Thin Film Devices

Yukinori Morita, AIST
Yi Yang, Tsinghua Univ.
7A-1   14:30-14:55

Origin of High Mobility in InSnZnO MOSFETs, Nobuyoshi Saito, Tomomasa Ueda, Tsutomu Tezuka, and Keiji Ikeda, Toshiba Memory Corporation

7A-2   14:55-15:20

Suppression of Channel Shortening Effect for InGaZnO Thin-Film- Transistor by In-Sn-O Source/Drain Electrodes, Junji Kataoka, Nobuyoshi Saito, Tomomasa Ueda, Tsutomu Tezuka, Tomoaki Sawabe, and Keiji Ikeda, Toshiba Memory Corporation

7A-3   15:20-15:45

Radio-Frequency Superiority of Poly-Si TFTs with T-Shaped Gate and Air Spacers for IoT Applications, Z. Y. Yang1*, Y. A. Huang1**, H. C. Lin1+, P. W. Li1, K. M. Chen2, and G. W. Huang2, 1Institute of Electronics, National Chiao Tung University, 2National Nano Device Labs.

7A-4   15:45-16:10

The Analysis for OLED Property of the Devices with Various Aperture Ratio by Impedance Spectroscopy , Tomohiko Naganuma, Chun-Che Ma, Tohru Sasaki, Tsuyoshi Uemura, and Masaya Adachi, Japan Display Inc.

16:10-16:30 Authors Interview

16:30-17:30 Poster Viewing in Event Hall

*For Poster Session, please see the detailed information. (click here)

17:30-19:00 Women in Engineering / Young Professional Event in Room Valencia

Friday, March 16

Room A (Shinsho-Hall A)

8:30-10:10 Session 8A - Device: Super Steep Slope Devices 2

Yukinori Morita, AIST
Ken Uchida, Keio Univ.
8A-1   8:30-8:55

On the Dynamic Characteristics of Ferroelectric and Paraelectric FETs, Ashwani Kumar and M. M. De Souza, University of Sheffield

8A-2   8:55-9:20

Impact of Contact Resistance on 2D Negative-Capacitance FETs, Po-Sheng Lu, Wei-Xiang You, and Pin Su, National Chiao Tung University

8A-3   9:20-9:45

P-channel Super Steep Subthreshold Slope PN-Body Tied SOI FET: Possibility of CMOS, Takayuki Mori1, Jiro Ida1, Takahiro Yoshida1, and Yasuo Arai2, 1Kanazawa Institute of Technology, 2High Energy Accelerator Research Org.

8A-4   9:45-10:10

Device Designs of III-V Tunnel FETs for Performance Enhancements through Line Tunneling, Chiu-Ting Wang and Vita Pi-Ho Hu, National Central University

10:10-10:40 Authors Interview

Room B (Shinsho-Hall B)

8:30-10:10 Session 8B - Process: Ge Surface Process Control

Osamu Nakatsuka, Nagoya Univ.
Jiro Yugami, Hitachi Kokusai Electric Inc.
8B-1   8:30-8:55

Rigidity Enhancement of GeO2 by Y Doping for Reliable Ge Gate Stacks, Tomonori Nishimura1, Xiaoyu Tang1,2, Takeaki Yajima1, and Akira Toriumi1, 1The University of Tokyo, 2Nanjing University

8B-2   8:55-9:20

Anomalous Spectral Shape Evolution of Ge Raman Shift in Oxidation of SiGe, Y. Noma, W. Song, T. Nishimura, T. Yajima, and A. Toriumi, The University of Tokyo

8B-3   9:20-9:45 (Invited)

Interface Engineering of Ge-Based Nanoelectronics Using Fluorinated Graphene, Xiaohu Zheng1, Miao Zhang1, Xiaohua Shi1, Gang Wang1, Li Zheng1, Yuehui Yu1, Anping Huang2, Huang, Paul K. Chu3, Heng Gao4, Wei Ren4, Zengfeng Di1, and Xi Wang1, 1Chinese Academy of Sciences, 2Beihang University, 3City University of Hong Kong, 4Shanghai University

8B-4   9:45-10:10

Ge FinFET CMOS Inverters with Improved Channel Surface Roughness by Using In-Situ ALD Digital O3 Treatment, M.-S. Yeh1, G.-L. Luo1, F.-J. Hou1, P.-J. Sung1,2, C.-J. Wang1, C.-J. Su1, C.-T. Wu1, Y.-C. Huang1, T.-C. Hong1,2, T.-S. Chao2, B.-Y. Chen1, K.-M. Chen1, M. Izawa3, M. Miura3, M. Morimoto3, H. Ishimura4, Y.-J. Lee1, W.-F. Wu1, and W.-K. Yeh1, 1National Nano Device Laboratories, 2National Chiao Tung University, 3Hitachi High-Technologies Corporation, 4Hitachi High- Technologies Taiwan Corporation

10:10-10:40 Authors Interview

Room C (Conference Room 3)

8:30-9:20 Session 8C - Featuring: Nanotechnology Featuring the 2D Materials 1

Iriya Muneta, Tokyo Tech.
Navakanta Bhatt, Indian Institute of Science
8C-1   8:30-8:55(Invited)

The Auger FET: A Novel Device Concept for Subthermal Switching, James T. Teherani, Columbia University

8C-2   8:55-9:20

A Graphene Platform on Silicon for the Internet of Everything, Neeraj Mishra1, Sai Jiao1, Anjon Mondal1, Zulfiqar Khan1, John J. Boeckl2, Kurt D. Gaskill3, Ryan E. Brock4, Reinhold H. Dauskardt4, and Francesca Iacopi1, 1University of Technology Sydney, 2Air Force Research Laboratories, 3Naval Research Laboratory, 4Stanford University

9:20-10:40 Authors Interview

Room A (Shinsho-Hall A)

10:40-11:55 Session 9A - Device: Advanced Memory

Jae-Kyu Lee, Samsung
Jong-Ho Lee, Seoul National Univ.
9A-1   10:40-11:05

Ultra-High-Efficient Writing in Voltage-Control Spintronics Memory(VoCSM); the Most Promising Embedded Memory for Deep Learning, Y. Ohsawa, H. Yoda, N. Shimomura, S. Shirotori, S. Fujita, K. Koi, B. Altansargai, S. Oikawa, M. Shimizu, Y. Kato, T. Inokuchi, H. Sugiyama, M. Ishikawa, T. Ajay, K. Ikegami, S. Takaya, and A. Kurobe, Toshiba Corporation

9A-2   11:05-11:30

Experimental and Simulation Study of Resistive Switching Properties in Novel Cu/Poly-Si/TiN CBRAM Crossbar Device, Umesh Chand1, Den Berco2, Ren Li1, Meshal Alawein1, and Hossein Fariborzi1, 1King Abdullah University of Science and Technology, 2Nanyang Technological University

9A-3   11:30-11:55

Reconfigurable Cell String Having FET and Super-Steep Switching Diode Operation in 3D NAND Flash Memory, Nagyong Choi1, Ho- Jung Kang1, Sung-Min Joe2, Byung-Gook Park1, and Jong-Ho Lee1, 1Seoul National University, 2Samsung Electronics Co., Ltd.

11:55-12:10 Authors Interview

Room B (Shinsho-Hall B)

10:40-11:55 Session 9B - Package: Fan-Out Technology

Yoichiro Kurita, Toshiba Corp.
Piyush Gupta, Qualcomm
9B-1   10:40-11:05 (Invited)

The Evolution of Panel Level Packaging, R. Aschenbrenner, M. Töpper, T. Braun, and A. Ostmann, Fraunhofer Institute for Reliability and Microintegration

9B-2   11:05-11:30

Development of Semiconductor Manufacturing System Integrating Wafer Process and Packaging Process Using a Half-Inch Sized Package, Fumito Imura1,2, Michihiro Inoue1, Arami Saruwatari1, Sommawan Khumpuang1,2, and Shiro Hara1,2, 1National Institute of Advanced Industrial Science and Technology (AIST), 2Minimal Fab General Incorporated Association

9B-3   11:30-11:55

A Novel System-in-Package Using High-Density Fan-out Technology for Heterogeneous Integration, SeungNam Son1, HoDol Yoo1, Ji Hyun Kim1, JooHyun Kim1, DooWon Lee1, WonChul Do1, Yun Ra2, KwangSup So2, WooHyun Paik2, and KangWook Lee1, 1Amkor Technology Korea, 2LG Electronics, Inc.

11:55-12:10 Authors Interview

Room C (Conference Room 3)

10:40-11:55 Session 9C - Featuring: Nanotechnology Featuring the 2D Materials 2

Iriya Muneta, Tokyo Tech.
Navakanta Bhatt, Indian Institute of Science
9C-1   10:40-11:05 (Invited)

2D Electronics – A Promising Option or a Type C Hype Cycle?, Frank Schwierz, Technische Universität

9C-2   11:05-11:30 (Invited)

New Device Concepts, Transistor Architectures and Materials for High Performance and Energy Efficient CMOS Circuits in the Forthcoming Era of 3D Integrated Circuits, D. Esseni1, O. Badami1, F. Driussi1, D. Lizzit1, M. Pala2, P. Palestri1, T. Rollo1, L. Selmi1, and S. Venica1, 1University of Udine, 2Université Paris-Sud

9C-3   11:30-11:55 (Invited)

Device Performance of 2D Layered Material Transistors and Their Challenges: A Theoretical Study, Gengchiau Liang, National University of Singapore

11:55-12:10 Authors Interview

Room D (Barcelona)

10:00-12:20 Symposium on Frontier Researches of Functional Oxide Devices and Materials

Room A (Shinsho-Hall A)

13:30-13:40 Poster Award Ceremony

13:40-15:20 Session 10A - Yield & Manufacturing: Yield Analysis and Improvement

Bill Nehrer, Consultant
Angelo Pinto, Qualcomm
10A-1   13:40-14:05 (Invited)

Short Flow Characterization Vehicle (Test Chip) Usage in Advanced Technology Development and Yield Improvement, Tomasz Brozek, PDF Solutions

10A-2   14:05-14:30 (Invited)

Fast Defect Reduction to Enable Customer Yield Ramp, Roman Mostovoy and Suketu Parikh, Applied Materials

10A-3   14:30-14:55

Particle Removal Characteristics in Liquid Flow during Wafer Rotation, Naoyuki Handa1, Satomi Hamada1, Masayoshi Imai1, Yutaka Wada1, Hiroshi Sobukawa1, Hirokuni Hiyama1, and Kenji Amagai2, 1Ebara Corporation, 2Gunma University

10A-4   14:55-15:20 (Invited)

Trends in Manufacturing Productivity and Yield Enhancement for Interconnected Devices and Industries, Rebecca Mih, Lam Research

15:20-15:40 Authors Interview

Room B (Shinsho-Hall B)

13:40-15:20 Session 10B - Material: Materials Transistors

Paul Berger, Ohio State Univ.
Yang Xu, Zhejiang Univ.
10B-1   13:40-14:05

Single-Fabrication-Step Ge Nanosphere/SiO2/SiGe Heterostructures: A Key Enabler for Realizing Ge MOS Devices, Po-Hsiang Liao1, Kang- Ping Peng2, Chia-Tsong Chen2, Horng-Chih Lin2, Tom George1, and Pei- Wen Li1,2, 1National Central University, 2National Chiao Tung University

10B-2   14:05-14:30


10B-3   14:30-14:55

The Sub-Micron GaN HEMT Device on 200mm Si(111) Wafer with Low Wafer Bow, Chieh-Chih Huang1, Zhihong Liu1, Weichuan Xing1, Geok Ing Ng2, Eugene A Fitzgerald3, Soo Jin Chua4, 1LEES, Singapore- MIT Alliance for Research and Technology, 2Nanyang Technological University, 3Massachusetts Institute of Technology, 4National University of Singapore

10B-4   14:55-15:20 (Invited)

Flexible Printed Organic Thin-Film Transistor Devices and IoT Sensor Applications, Shizuo Tokito, Yamagata University

15:20-15:40 Authors Interview

Event Hall

Wednesday, March 14 14:55-15:30, 16:45-18:00
Thursday, March 15 13:30-14:30, 16:30-17:30

Poster Session

Thermal-Performance Improvement of Collector-Up Heterojunction Bipolar Transistors by Graphene Packaging, W. L. Su and H. C. Tseng, Kun Shan University


Analysis of Temperature Distribution in Stacked IC with Three Tier Structure, Satoshi Ushida1, Yuri Mukai1, Toshihiro Matsuda1, Hideyuki Iwata1, Tomoyuki Hatakeyama1, and Takashi Ohzone2, 1Toyama Prefectural University, 2Dawn Enterprise Co., Ltd.


Device Design Parameter for Desired DC Gain and Hysteresis- Free FDSOI NCFETs, Shruti Mehrotra and S. Qureshi, Indian Institute of Technology, Kanpur


Ferroelectric Characteristics of Ultra-Thin Hf1-xZrxO2 Gate Stack and 1T Memory Operation Applications, M. H. Lee1, C.-Y. Kuo1, C.-H. Tang1, H.-H. Chen1, C.-Y. Liao1, R.-C. Hong1, S.-S. Gu1, Y.-C. Chou1, Z.- Y. Wang1, S.-Y. Chen1, P.-G. Chen1,2, M.-H. Liao2, and K.-S. Li3, 1National Taiwan Normal University, 2National Taiwan University, 3National Nano Device Laboratories


Embedded Tunable Near Infrared Sensor with Programmable Potential Barrier on Nano-Meter CMOS Platforms, Zih-Hong Chen1, Chien-Ping Wang1, Po-Hsiang Huang1, Yue-Der Chih2, Jonathan Chang2, Chrong Jung Lin1, and Ya-Chin King1, 1National Tsing Hua University, 2Taiwan Semiconductor Manufacturing Company


Potential and Limitations of HfZrO2-Based Ferroelectric MOSFET for Low Power Applications, Yang Li1, Yuye Kang1, Yi Tong2, and Xiao Gong1, 1National University of Singapore, 2Nanjing University of Posts and Telecommunication


Paraelectric-Ferroelectric Transition in Hafnium-Oxide-Based Ferroelectric Memory, Chia-Chi Fan1, Yu-Chien Chiu1, Chien Liu1, Wen-Wei Lai1, Chun-Yuan Tu1, Ming-Huei Lin1, Tun-Jen Chang1, Chun- Yen Chang1, Guan-Lin Liou2, Hsiao-Hsuan Hsu3, Cheng-Yu Tang3, and Chun-Hu Cheng4, 1National Chiao Tung University, 2National Tsing Hua University, 3National Taipei University of Technology, 4National Taiwan Normal University


Thermoelectric Characteristics of Rapid-Melting-Grown SiGe Wires Measured by Peltier Cooling Experiment, Shuichiro Hashimoto1, Kouta Takahashi2,3, Shunsuke Oba1, Takuya Terada1, Masataka Ogasawara1, Motohiro Tomita1,3, Masashi Kurosawa2,4, and Takanobu Watanabe1, 1Waseda University, 2Nagoya University, 3JSPS Research Fellow, 4JST-PRESTO


Cryogenic Characteristics of Ge Channel Junctionless Nanowire Transistors, Chuanchuan Sun, Renrong Liang, Lei Xiao, Libin Liu, Jun Xu, and Jing Wang, Tsinghua Universi


1.0 THz Detection by InAs Quantum-Well MOSHEMT Using GSG THz Probe, Eiji Kume1, Hiroyuki Ishii2, Hiroyuki Hattori2, Wen-Hsin Chang2, Yuichi Mukai3, Mutsuo Ogura1, Haruichi Kanaya3, Tanemasa Asano3, and Tatsuro Maeda2, 1IRspec Corporation, 2AIST, 3Kyushu University


Design and Performance of π-Type Thin-Film Nano/ Micro-TEG Using Vacuum/SiO2-Hybrid Insulation Module Structure, Toshimasa Seino, Nana Chiwaki, Suzune Yamashita, and Satoshi Sugahara, Tokyo Institute of Technology


Dynamic Thermal Characterization of Microheater in Semiconductor Metal Oxide Based Gas Sensor, Ravi Shankar1, Olivier Le Neel1, Fang Xing Yuan2, Shian Yeu Kam1, and Tien Choy Loh1, 1STMicroelectronics Pte Ltd., 2National University of Singapore


Multibit Memory Cells Based on Spin-Orbit Torque Driven Magnetization Switching of Nanomagnets with Configurational Anisotropy, Shaik Wasef, Selma Amara, Meshal Alawein, and Hossein Fariborzi, King Abdullah University of Science and Technology (KAUST)


Implications of 3-Dimensional Scaling Rules on a 1.2 kV Trench Clustered IGBT, Peng Luo, Hong Yao Long, Mark R. Sweet, M. De Souza, and E. M. S. Narayanan, The University of Sheffield


Mems Fluxgate Magnetometer Whose Solenoid Coil Are Winded by a Novel Wafer-Level Liquid Alloy Filling Method, Jiebin Gu1, Xiaowei Hou2, Xiaoyuan Xia1, Weibo Zhang1, and Xinxin Li1, 1Shanghai Institute of Microsystem and Information Technology, 2Ningbo CRRC Times Transducer Technology Co., Ltd.


Quadrupole-Electrode-Integrated Micropores for Selective Single-Particle Detections, Tomoki Hayashida, Takahito Ohshiro, Makusu Tsutsui, and Masateru Taniguchi, Osaka University


Domain Size Effects on Thermoelectric Properties of P-Type Ge0.95Sn0.05 Layers Grown on GaAs and Si Substrates, Yukihiro Imai1, Kouta Takahashi1,2, Noriyuki Uchida3, Tatsuro Maeda3, Osamu Nakatsuka1, Shigeaki Zaima1, and Masashi Kurosawa1,4, 1Nagoya University, 2JSPS Research Fellow, 3National Institute of Advanced Industrial Science and Technology (AIST), 4JST-PRESTO


Low Thermal Budget Fabrication of Poly-Ge1-xSnx Thin Film Thermoelectric Generator, Kouta Takahashi1,2, Hiroshi Ikenoue3, Mitsuo Sakashita1, Osamu Nakatsuka1,4, Shigeaki Zaima1, and Masashi Kurosawa1,4, 1Nagoya University, 2JSAP Research Fellow, 3Kyushu University, 4JST-PRESTO


HAXPES Evaluation of Ferroelectric HfSiO MIM Capacitor, Koji Usuda, Yuuichi Kamimuta, Shoichi Kabuyanagi, Masahiko Yoshiki, Mitsuhiro Tomita, and Masumi Saitoh, Toshiba Corporation


Cu Cone Inserted CBRAM Device Fabrication and Its Improved Switching Reliability Induced by Field Concentration Effect, Hae Jin Kim1, Tae Hyung Park1, Kyung Jean Yoon1, Gil Seop Kim1, Tae Jung Ha2, Soo Gil Kim2, and Cheol Seong Hwang1, 1Seoul National University, 2SK Hynix Inc.


Study on the Effect of Hf Oxide Film Sputtering Condition on Resistive Random Access Memory Properties, A. Azuma, R. Nakajima, H. Yoshida, T. Shimizu, T. Ito, and S. Shingubara, Kansai University


Novel Technique for Production-Yield Enhancement of Semiconductor Devices, Shiro Ninomiya, Yoji Kawasaki, Yasuharu Okamoto, Kazuhisa Ishibashi, Toshio Yumiyama, Akihiro Ochi, Yusuke Ueno, Hiroyuki Kariya, Mitsuaki Kabasawa, and Mitsukuni Tsukihara, Sumitomo Heavy Industries Ion Technology Co., Ltd. (SMIT)


High Aspect Ratio InAs Fins Fabrication with Sub-30nm Fin Width for FinFETs, Maneesha Rupakula1, Clarissa Convertino2, Heinz Schmid2, Kirsten Moselund2, and Adrian Mihai Ionescu1, 1Ecole Polytechnique Fédérale de Lausanne, 2IBM Research - Zurich


Position Control and Gas Source CVD Growth Technologies of 2D MX2 Materials for Real LSI Applications, T. Irisawa1, N. Okada1, W. Mizubayashi1, T. Mori1, W. H. Chang1 , K. Koga1, A. Ando1, K. Endo1, S. Sasaki2, T. Endo2, and Y. Miyata2, 1National Institute of Advanced Industrial Science and Technology (AIST), 2Tokyo Metropolitan University


Annealing Effect on Amorphous Indium-Zinc-Tungsten-Oxide Thin-Film Transistors, Ruofan Fu1, Jianwen Yang1, Qun Zhang1, Wei-Chiao Chang2, Chien-Min Chang2, Po-Tsun Liu2, and Han-Ping D. Shieh2, 1Fudan University, 2National Chiao Tung University


Atomic Layer Deposition(ALD) of Ru Thin Film on Ta2O5/Si Substrate Using RuO4 Precursor and H2 Gas, Cheol Hyun An, Sang Hyeon Kim, Dae Seon Kwon, Soon Hyung Cha, Sung Tak Cho, and Cheol Seong Hwang, Seoul National University


Effect of Activation and Stress Conservation in Si0.7Ge0.3:B after Two-Step Microwave Annealing, Tai-Chen Kuo and Wen-His Lee, National Cheng Kung University


Analysis of DC Self Heating Effect in Stacked Nanosheet Gate-All- Around Transistor, Min Jae Kang1, Ilho Myeong2, Myounggon Kang3, and Hyungcheol Shin2, 1Imperial College London, 2Seoul National University, 3Korea National University of Transportation


Self-Heating-Effect-Free p/n-Stacked-NW on Bulk-FinFETs and 6T-SRAM Layout, Eisuke Anju, Iriya Muneta, Kuniyuki Kakushima, Kazuo Tsutsui, and Hitoshi Wakabayashi, Tokyo Institute of Technology


Physics-Based Compact Modeling of MSM-2DEG GaN-Based Varactors for THz Applications, Ahtisham Ul Haq Pampori1, Sheikh Aamir Ahsan1, Sudip Ghosh1, Sourabh Khandelwal2, and Yogesh Singh Chauhan1, 1Indian Institute of Technology, Kanpur, 2Macquarie University


Body Bias Dependence of Hot Carrier Degradation (HCD) in Advanced FinFET Technology, Jiayang Zhang1, Zixuan Sun2, Runsheng Wang1, ZhuoqingYu1, Pengpeng Ren1, and Ru Huang1, 1Peking University, 2Fuzhou University

Posters from Seifu Nankai High School

Students from Seifu Nankai High School will deliver poster presentations on research themes, including such topics as "Scenario Planning".

  • Introduction of Seifu Nankai Jr. & Sr. High School
  • Scenario Planning "Smart House in 2030"
  • Perovskite Solar Cells -The New Star of Our Future-