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Vijay Angarai completed his BE degree in Computer Eng. from Victoria Jubilee Technical Institute, India and his MS degree in Electrical Engineering from University of Texas at Dallas. He currently works with the Advanced DSP group in LSI Logic, Dallas. His research interests include signal processing architectures, computer arithmetic and low power design methodology.
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Educational background:
B.S., Physics, Texas A&M University, May 1983
M.S., Electrical Engineering, Texas A&M University, December 1988
Ph.D., Electrical Engineering, Texas A&M University, December 1999
Professional experience:
Assistant Professor, Electrical Engineering, The University of Texas
at Dallas, September 2000 to present.
Visiting Assistant Professor, Electrical Engineering, The University
of Texas at Dallas, September 1999 to August 2000.
Assistant Professor, Engineering Technology, Texas A&M University,
September 1992 to August 1999.
Technical Consultant, September 1992 to present.
Training Specialist, Texas Engineering Extension Service (TEEX), July
1985 to August 1992.
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Randy Geiger received the Ph.D. Degree in Electrical Engineering from
Colorado State University in 1977. From 1977 to 1990 he was a faculty member
in the Electrical Engineering Department at Texas A&M University. He
has been affiliated with the Department of Electrical and Computer Engineering
at Iowa State University since 1990 and currently holds the title of Willard
and Leitha Richardson Professor. Dr. Geiger?s teaching and research interests
are in the area of analog and mixed-signal VLSI design with particular
emphasis on data converters, amplifiers, high-speed communication circuits,
BIST, and statistical modeling and design of mixed-signal systems for yield
enhancement. Dr. Geiger is a past President of the IEEE Circuits and Systems
Society and a past member of both the IEEE Publications Board and the IEEE
Periodicals Council. He is a Fellow of IEEE and received the IEEE Millenium
Medal in 2000.
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Vijay Reddy is a Member of the Group Technical Staff at Texas Instruments,
Dallas, Texas. He received his Ph.D. in Electrical Engineering in 1994
from the University of Texas at Austin. He joined TI in 1994 and has worked
on dielectric reliability, ESD, Latch-up, plasma charging, transistor reliability,
and mobile ion testing of logic and DRAM technologies. Since 1998 he has
focused on transistor and circuit reliability in sub-0.13um logic and embedded
memory technologies. More recently his activities have included product
reliability and qualification methodologies. He has published more than
20 papers and has several patents filed. He is serving as the Chair of
the Device and Process Committee of the 2003 IRPS (International Reliability
Physics Symposium) and has presented a tutorial on CMOS Reliability at
IRPS.
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John W. Fattaruso grew up in Berkeley, CA, and received the B.S.(highest honors), M.S., and Ph.D. degrees in electrical engineering from the University of California, Berkeley, through 1986. He has been a Hertz Foundation Fellow, Teaching Associate, Research Assistant and Instructor at the University of California, Berkeley. In 1979 he worked in the Digital Signal Processing R&D group at Hewlett-Packard, Santa Clara, CA, and in 1985 he served as a consultant to Seeq Technology, San Jose, CA. Since 1987 he has been with various research and product development departments of Texas Instruments, Dallas, TX, working on analog VLSI technology. He was elected Distinguished Member of Technical Staff in 2001. His research interests include analog and RF circuit design, circuit simulation and optimization, neural networks and numerical analysis. He currently holds 23 patents in circuit design, has authored or co-authored 20 conference and journal papers, and has served on the analog program subcommittee of the ISSCC and as guest editor of the JSSC. Dr. Fattaruso is a member of Eta Kappa Nu, Tau Beta Pi and Phi Beta Kappa.
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Jason Binney is a Sr Staff Corporate Application Engineer and has been working at Synopsys since 1995. His current primary responsibilities have been with Physical Compiler and collaborating in technology partnership with some of Synopsys's key customers to provide requirements as the technology nodes move to deeper sub micron geometries. Recently his related work has focused on design closure with Signal Integrity in the Implementation flows from RTL2GDSII including pilot programs and tapeout projects with these capabilities.
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Program Summary:
Why choose flip chip?
I. Design Requirements that Drive to FlipChip
a. Large numbers of IO
b. Large numbers of Power/Gnd connections
c. High Performace Packaging
d. High Power Consumption
e. Nomimal Die Size
f. Multiple Power Supplies
II. Tradeoffs in FlipChip
a. Peripheral Bumps vs. Full Array
b. Peripheral IO vs. Core Array IO
III. CAD Problems to be Solved
a. IO Design
b. IO Placement
c. Single/Multiple Power Grids
d. Place and Route
e. Connectivity Checking
f. CoDesign of PCB, Substrate and Silico
Scott Wood
Graduated from University of Houston, TX, in 1984.
Texas Instruments 1978 - 1984 as:
Equipment Engineering (Production
Fab)
Product/Test Engineering
(Microcomputers)
ST Microelectronics 1984 - present as:
Product/Test Engineering
Retical Engineering for
worldwide deployment
Design Manager, Digital
Backend Team
Design Support Manager Central
R&D, Region Americas
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Program Summary:
Sigma-delta converters have been conventionally used for low-bandwidth
and high resolution. Recent results show that complex structures can
achieve
relatively high resolution while using a low oversampling ratio.
Therefore,
extending the signal bandwidth to the MHz bandwidth range enable using
sigma-delta techniques to an increasing number of communication
applications.
This talk discusses band and resolution needs of modern communication
schemes.
Then, it reviews the sigma-delta techniques and finally it presents
some
recent results published in the literature and on-going studies on the
topic carried on by students at the Analog Integrated Circuits and
Sensors
Laboratory, EE Department UT Dallas. It will be shown that, low-pass
ADC
with 2MHz band capable to satisfy the WCDMA specs consuming less than 4
mW and that 5 MHz band-pass ADC with 80 MHz IF and 80 dB SNR are
achievable
with modern CMOS technologies.
Biography:
Franco Maloberti has actively served the IEEE and the CAS Society since
1995. Currently he is a member of the CAS Board of Governors. In the
past
he has served as CAS Vice President for Region 8. He has chaired 1 CAS
conference, 2 CAS Workshops and guest edited 2 IEEE-TCAS II special
issues.
He is the President of the IEEE Sensor Council and he was the general
Chair
of the IEEE Sensors Conference in 2002.
Franco Maloberti is the Microelectronics Chair at the University of Dallas and Professor at the University of Pavia. Previously he was the inaugural holder of the TI J. Kilby Chair Professor of Engineering and professor of electrical engineering at the Texas A&M University. He has published more than 280 articles, three books and holds 16 Patents. He received the 1999 IEEE CAS Society Meritorious Service Award, the 2000 CAS Society Golden Jubilee Medal, and the IEEE Millenium Medal. Franco Maloberti received his university education from the Parma University, Italy(Laurea with Laudem). He received the Ph.D. Honoris Causa from INAOE, Puebla, Mexico. He is a Fellow of IEEE.
rogram Summary:
The shared-memory based packet switches are known to provide the best
possible throughput performance for bursty data traffic in high-speed packet
networks and Internet compared with other buffering schemes under conditions
of identical memory resources deployed in the switch. However, scaling of
shared-memory based switches to a larger size has been a challenge for
researchers in the switching field, mainly due to the physical limitations
imposed by the memory-access speed and the centralized control for switching
functions in shared-memory switches. In this seminar, a new class of switching
architecture called the sliding-window switch that is aimed at overcoming these
bottlenecks will be presented. Comparative performance of the class of sliding-window
switch will also be discussed.
Biography:
Dr. Sanjeev Kumar is involved in academic & industrial research & development,
and teaching in the area of Network Security, Broadband Wireline and Wireless
Data Networks, Digital Systems, Computer Architecture, and Hardware/Software
design in the Department of Electrical Engineering at the University of Texas,
Edinburg, TX. Before joining UTPA, Dr. Kumar worked with the leading networking
companies in the US. In the networking industry, Dr. Kumar played an active
role in strategic planning, engineering & development of new broadband switch
devices, equipment and networks; Performance evaluation of broadband multiservice
networks and protocols; Internetworking of wireline & wireless networks.
Dr. Kumar's current research interests include all aspects of Network Security,
Router Design, Internet architecture, Internet routing/switching protocols,
Traffic engineering, Performance Evaluation, Optical switching, DWDM optical networks, Storage Area Networks, Wireless Ad Hoc and Sensor Networks.
Dr. Kumar has authored over 30 technical papers. Dr. Kumar's research findings
have been cited by other researchers in the field. Dr. Kumar has served as a
member of technical program committee for international conferences and
reviewed research papers for leading networking conferences and journals.
He has been awarded US patent for his inventions in the area of broadband
networks. Dr. Kumar received the Ph.D. degree in Computer Engineering from
North Carolina State University, Raleigh, North Carolina. He is a Senior member of IEEE.
