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Date: 3rd March, 2024

Time: 9 am – 6 pm

Tutorial 1: Power and Energy Devices (PED)

Session Chair : Prof. Sushobhan Avasthi

1) GaN power transistor: Technology and Applications


GaN power transistors are waited long time for high switching speed and high efficiency as the power supply application ranging from sub-100W to multi-kW. Small and cool USB type-C adapter with GaN is already available everywhere. Introduction of GaN to the power supply of data center server was earlier than USB type-C adapter. Recently, OBC and DC-DC for EV are considered as the promising application. Motivation for GaN is small form factor and high efficiency for these applications.

In this tutorial, structure, benefit, quality & reliability and application of GaN are presented. There are two types GaN are in the market. One is Cascode GaN, another is p-GaN E- mode. Comparison of two types is given. SiC is already in the market as high efficiency power switch. Pros and Cons of GaN and SiC are also discussed.

Ken Shono (Transphorm Inc., USA)

  • 1979: MS degree of Applied Physics, Osaka University, Japan
  • 1979 - 2010: Engaged in reliability physics of Si semiconductor. Investigated electromigration, hot carrier degradation, time dependent dielectric breakdown, soft error, stress-migration of aluminum and copper wire
  • 2010 - 2014: Development of GaN power transistor in Fujitsu Semiconductor Limited
  • 2014 - now: Quality assurance in Transphorm Inc.

2) Gallium nitride microwave/RF transistors: from fundamentals to emerging trends


GaN HEMTs operating in the microwave, primarily on SiC substrates, are fast penetrating the cellular infrastructure and the strategic markets as these devices enable power amplifiers with unrivalled performance. Although GaN RF HEMTs have been investigated for about 30 years now and are commercially available for more than two decades, yet, the research frontiers on the same and commercial prospects today are more promising than ever.

In this tutorial, first, we'll walk through the basics of a GaN RF HEMT keeping the focus on practical issues that are relevant for technology such as the effect of substrate, dislocations, compensation doping, device dimensions, passivation etc. We shall also discuss how various device dimensions and material/device properties affect various device parameters, and how those in turn, affect the performance of a power amplifier. How the device design and various aspects of it evolve with the need for power at higher frequencies, will also be touched upon.

Next, we shall transition to multi-finger HEMTs with high absolute output powers because these are the devices that go into real-world systems. Since most research publications and reports on GaN HEMTs are based two-finger devices only, a large part of the know-how pertaining to how to realize multi-finger GaN RF HEMTs is often strategic in nature and also proprietary, and hence, not published.

Finally, emerging trends in GaN RF devices will be discussed with respect to the literature. These include GaN on silicon for low-power applications - especially E-mode devices, N-polar GaN for W-band, ultrathin barrier and buffer-free HEMTs, and approaches to realizing GaN HEMTs with better linearity. Future challenges and opportunities for GaN HEMT will also be discussed.

Digbijoy Nath (IISc Bangalore)


Digbijoy Nath completed his PhD at Ohio State University in the dept. of Electrical and Computer Engineering, working in the area of MBE growth and novel devices in the III- nitrides material system. Thereafter, he joined Indian Institute of Science (IISc) Bengaluru in its Centre for Nano Science & Engineering where he is currently an Associate Professor. His group works on GaN-based transistors for power and microwave applications besides exploring gallium oxide-based diodes and photodetectors. He is a co-founder of AGNIT Semiconductors Pvt. Ltd. which is India's only startup on GaN HEMT design and manufacture, and he is also a co-PI of GEECI aka Gallium Nitride Ecosystem Enabling and Incubation Center, a small-volume gallium nitride fab, characterization and packaging facility which is funded by the Ministry of Electronics and IT, Govt. of India, and being set up at IISc under FSID.

Tutorial 2: Devices and Circuit Reliability (DCR)

Session Chair : Dr. Taiki Uemura

1) 2D Device Reliability


Insulators for Devices based on 2D Materials

Despite the breathtaking progress already achieved for 2D electronic devices, they are still far from exploiting their predicted performance potential. This is in part due to the lack of scalable insulators, which would go along with 2D materials as nicely as SiO2 goes with silicon. As a result, there is still no commercially competitive 2D transistor technology available today.

The selection of suitable insulators for 2D nanoelectronics represents an enormous challenge. However, this problem is of key importance, since scaling of 2D semiconductors towards sub-10nm channel lengths is only possible with gate insulators scalable down to sub-1nm equivalent oxide thicknesses (EOT). In order to achieve competitive device performance, these insulators need to meet stringent requirements regarding (i) low gate leakage currents, (ii) low density of interface traps, (iii) low density of border insulator traps and (iv) high dielectric strength.

The insulators typically used for 2D electronic devices are amorphous 3D oxides known from Si technologies (SiO2, HfO2, Al2O3), while native 2D oxides (MO3, WO3 and Bi2SeO5), layered 2D crystals (hBN, mica) and ionic 3D crystals (CaF2 and other fluorides like SrF2, MgF2) have received increasing attention. 3D oxides often form poor quality interfaces with 2D semiconductors and contain border traps which severely perturb stable device operation. Native oxides, on the other hand, are often non-stoichiometric due to the lack of well-adjusted oxidation methods and thus have a limited dielectric stability and inherently narrow bandgaps. As the most popular candidate, the layered 2D insulator hBN forms excellent van der Waals interfaces with 2D semiconductors, but has mediocre dielectric properties resulting in excessive leakage currents for sub-1nm EOT. The potential of other 2D insulators (e.g. mica) is currently unclear, in part due to the absence of scalable growth techniques. Finally, very promising insulators for 2D electronics are 3D ionic crystals like CaF2 which form well-defined interfaces to 2D channel materials. In contrast to hBN, fluorides have good dielectric properties and thus exhibit low gate leakage currents. This talk will address the current state of the art and summarize the main problems together with potential solutions.

Tibor Grasser (TU Wien)

  • Prof. Tibor Grasser is an IEEE Fellow and head of the Institute for Microelectronics at TU Wien. He has edited various books, e.g. on the bias temperature instability, hot carrier degradation, and low-frequency noise (all with Springer), is a distinguished lecturer of the IEEE EDS, has been involved in outstanding conferences such as IEDM (General Chair 2021), IRPS, ESSDERC (TPC Co-Chair 2015), IIRW (General Chair 2014), and SISPAD (General Chair 2007), is a recipient of the Best and Outstanding Paper Awards at IRPS (2008, 2010, 2012, and 2014), IPFA (2013 and 2014), ESREF (2008) and the IEEE EDS Paul Rappaport Award (2011). He currently serves as an Associate Editor for IEEE T-ED, following his assignment with Microelectronics Reliability (Elsevier).

2) A Device to Circuit Framework for Aging (BTI, HCD) in Advanced Technology Nodes


FETs in advanced logic circuits degrade over usage time due to Bias Temperature Instability (BTI) and Hot Carrier Degradation (HCD). In this short course, we will discuss about the following topics:

  • 1) Characterization of BTI and HCD, recovery, impact of measurement delay
  • 2) BTI Analysis Tool (BAT) framework related analysis of measured BTI data - estimation of end of life (EOL), process impact of BTI
  • 3) Hot Carrier Analysis Tool (HCAT) framework related analysis of measured HCD data - decoupling of BTI and HCD, impact of Self Heating
  • 4) TCAD for reliability - BTI and HCD simulation
  • 5) Circuit analysis for aging due to BTI and HCD, using Circuit Aging Reliability Analysis Tool (CARAT), demonstration of a seamless TCAD to SPICE framework

Souvik Mahapatra (IIT Bombay)

  • Souvik Mahapatra is currently the PK Kelkar chair professor in the Department of Electrical Engineering at Indian Institute of Technology Bombay. His research area is reliability of logic and memory devices and circuits. He interacts closely with several industries (fab tool, EDA, IDM, fabless) in the semiconductor ecosystem. He has published more than 150 articles in peer reviewed journals and conferences, written 22 book chapters, edited 2 books and delivered invited talks and tutorials in major IEEE conferences including IEDM and IRPS. He is a fellow of IEEE and of several Indian science and engineering academies (INSA, INAE and IASc).

Tutorial 3: Emerging computing paradigms for AI

Session Chair : Prof. Shubham Sahay

1) In-memory computing for artificial neural networks


Deep neural networks (DNNs) are transforming the landscape of artificial intelligence and serving as pivotal catalysts for advancements in device technology and computer architecture. Despite notable strides in creating specialized hardware for DNN inference, many existing architectures physically separate the memory and processing units. This results in DNN models being typically stored in a distinct memory location, necessitating a continuous transfer of data between the memory and processing units during computational tasks. This process hinders computation speed and imposes limitations on achieving optimal energy efficiency. Analog in-memory computing (AIMC) emerges as a promising solution to this challenge by incorporating two key principles inspired by the way biological neural networks function. In AIMC, synaptic weights are physically localized in nanoscale memory elements, and computational operations are executed in the analog/mixed-signal domain.

To begin, I will provide an introduction to Analog In-Memory Computing (AIMC) using non- volatile memory technology, emphasizing key concepts and related terminology. Following that, I will present a multi-tile mixed-signal AIMC chip designed for deep learning inference. Fabricated using 14nm CMOS technology, this chip features 64 AIMC cores/tiles built on phase-change memory technology. This presentation will serve as a foundation to explore the device, circuitry, architectural, and algorithmic aspects of AIMC in more detail. A key focus will be on achieving classification accuracy equivalent to floating point precision while conducting the majority of computations in the analog domain with relatively lower precision. In conclusion, I will discuss ongoing research efforts aimed at the next generation of AIMC chips and offer insights into the future outlook of this technology.

Abu Sebastian (IBM Research Zurich, Switzerland)

  • Dr. Abu Sebastian is a Distinguished Scientist and technical manager at IBM Research - Zurich. He is one of the technical leaders of IBM's research efforts towards next generation AI Hardware and manages the in-memory computing group at IBM Research - Zurich. He is the author of over 200 publications in peer-reviewed journals/conference proceedings and holds over 90 US patents. In 2015 he was awarded the European Research Council (ERC) consolidator grant and in 2020, he was awarded an ERC Proof-of- concept grant. He was an IBM Master Inventor and was named Principal and Distinguished Research Staff Member in 2018 and 2020, respectively. In 2019, he received the Ovshinsky Lectureship Award for his contributions to "Phase-change materials for cognitive computing". In 2023, he was conferred the title of Visiting Professor in Materials by University of Oxford. He is a distinguished lecturer and fellow of the IEEE.

2) Biologically realistic artificial neural networks (SNNs)


Spiking neural networks (SNNs) are network architectures largely inspired by biological neural connectivity. They aim to mimic information processing pathways observed in brain through implementation component behavior (neurons, synapses) as well learning mechanisms. The networks typically feature distributed memory architecture. Owing to information encoding in spikes, these networks offer promise for extremely low power processing. Bio-realistic implementation of SNNs in hardware is done in analog/mixed-signal domain. Recent development of nano-scale memories with multi-level memory tunability has allowed area and power efficient implementation of synapses and neurons in SNNs. It has provided a promising approach to develop high-computational capacity SNN hardware.

I will first introduce basics of SNNs highlighting the bio-realistic elements in their implementation and some of the learning/training mechanisms employed. Then, I will briefly touch upon SNN hardware implementation examples. I will present implementation of quantum tunnelling based neuron and SNN implementation in 45 nm CMOS technology. Thereafter, I will discuss various approaches and examples of implementation of neurons, synapses, and SNNs with unique properties of nanoscale non-volatile memory (NVM) devices in hybrid CMOS-NVM technology. I will conclude by discussing challenges and opportunities for NVM based implementation of SNNs.

Veeresh Deshpande (IIT Bombay)

  • Prof. Veeresh Deshpande is an Associate Professor at the Department of Electrical Engineering, IIT Bombay. He obtained a PhD in Applied Physics from CEA-LETI/University of Grenoble, France in 2012. After his PhD, he worked at IBM SRDC (India) from 2012-14. He was at IBM Research - Zurich from 2014-17, where his research work was focused on 3D integration, devices for neuromorphic systems, and Si qubits for quantum computing. From 2019-2023, he was deputy head of the institute and group leader at Helmholtz- Zentrum Berlin, where he led a research group on devices and hetero-integration of novel oxide materials such as ferroelectrics, oxide semiconductors with CMOS for neuromorphic computing. His current research interests include embedded non-volatile memories, neuromorphic computing, hetero-integration, and system-technology-co-optimization. He has authored several (>40) peer-reviewed journals/conference proceedings and filed around 20 patents. He is currently serving on the technical programme committee of IEEE IEDM and ESSERC.

Tutorial 4: Modeling and Simulation (MS)

Session Chair : Prof. Avinash Lahgere

1) TCAD based compact model parameter extraction of Silicon and SiliconCarbide High Power Devices


TCAD based process and device simulations can be used to understand semiconductor device electrical behaviour and optimize its performance for a given specifications by applying required structural and process related modifications. The analysis can be performed at a single device level or at a circuit level. However, the simulation turn-around-time increase as the number of circuit elements increases. For an efficient large scale circuit simulation, sub-circuit compact models can be derived by using standard models that are approved by Compact Model Coalition (CMC) as the standard models may not be able to capture all the physical effects of the new device structures.

In this tutorial, I would like to go through the steps in detail w.r.t. Process and Device simulation of power devices using Sentaurus TCAD – simulation of device characteristics required for extracting the model parameters of a given compact model. The compact model could be a standard model approved by CMC for high voltage power devices or a user-defined model based on sub-circuit modeling approach. Finally, will discuss on the validation aspects of the compact model before using it for the circuit design tasks.

Vinay Kumar (Synopsys)

  • Vinay Dasarapu received the M. Tech. and the Ph. D. degrees from the Indian Institute of Technology -- Bombay, in 2001 and 2005, respectively. His main interests are in the areas of semiconductor device modeling and simulation of advanced logic and high-power semiconductor devices. Experienced in developing optimized process and device simulation flows for RF and High-Power Energy efficient systems using WBG semiconductors. Skilled in building IoT/DeepLearning based smart products and worked on several projects developing large-scale machine learning models for complex image detection and NLP for embedded-system platforms (ARM-v7/v8).

2) Compact modeling: general introduction and modeling of statistical variability


Compact models are essential elements in a circuit design flow. They provide a full description of each integrated component's electrical properties as a function of their size, temperature, bias conditions, etc. To support complex circuit analyses and enable simulation of large-scale circuits, their computational burden must be small, yet they must provide accurate and consistent results.

In this tutorial, we will start by providing a general introduction to compact modeling. This includes the role of compact models in the design flow, challenges related to their development, and a quick overview of the main compact models that are used in the industry today.

Then, we will zoom in on the variability that inherently comes with semiconductor manufacturing. Accounting for this variability during circuit design is critical for the development of products with good fabrication yield. Consequently, it is critical that SPICE libraries not only accurately reflect the nominal behavior of the electrical components, but also capture the stochastic variations.

We will review the most commonly used methods to model variability in industrial SPICE libraries: fixed corners and Monte Carlo models. What are they based on, how are these models created, what modeling techniques are used, what do they represent, and - very important - what do they not represent? Special attention will be devoted to the intrinsic limitations of corner models.

Finally, we will discuss some lesser-known domains where variability modeling is very important: 1/f- noise and (passive) backend devices.

Gert-jan Smit (NXP Semiconductors)

  • Dr. Geert D.J. (Gert-Jan) Smit is a Technical Director in SPICE modeling with NXP Semiconductors in The Netherlands. He received MSc degrees in physics (1998) and mathematics (1999) from Utrecht University, The Netherlands. Subsequently, he received a PhD degree in physics from Delft University of Technology, The Netherlands, in 2004. After that, he joined Philips Research (later NXP Semiconductors) and has worked on a large variety of Compact-Modeling-related topics.
  • Gert-Jan was one of the key developers of the PSP model when it was standardized by the Compact Model Coalition (CMC) in 2005. Since then, he has been the NXP representative in the quarterly CMC meetings. He is a Senior Member of IEEE, he served in the technical program subcommittee (modeling and simulation) of the IEEE International Electron Device Meeting (IEDM), he is currently a member of the IEEE-EDS Compact Modeling Committee, and he authored and coauthored more than 50 papers in international scientific journals and conferences.
  • His current research interests include CMOS models (including RF), statistical modeling, and model integration in production-level tools & libraries.

3) MOSFET Characterization and Modeling for Cryogenic Applications


Quantum computers must operate at cryogenic temperature to preserve their quantum states. In existing prototypes, input signals and biases are generated outside the cryostat and routed to the quantum core through cables and output signals go in the opposite way. Wiring becomes critical with the increasing number of qubits. The straightforward solution consists of integrating microcontrollers in the cryostat alongside the quantum core. To enable the design of such complex electronic systems, standard compact models have recently been updated to operate at cryogenic temperatures including first low-temperature effects.

However, Process Design Kit (PDK) from foundries are still missing to allow robust cryogenic IC design. The aim of this tutorial is to provide an overview of today's measurement methods, latest reported cryogenic electrical behaviors and corresponding compact modeling strategies. Finally, we will discuss what is missing to get an operational PDK for IC design.

Thomas Bedecarrats (CEA Leti)

  • Thomas Bédécarrats received the M.S. and Ph.D. degrees in electrical engineering from Université Grenoble Alpes (UGA) in 2015 and 2019, respectively. He is currently research scientist and research engineer at CEA-Leti, being part of the compact modeling team in the simulation and modeling laboratory. Since 2015, his research focuses on FD-SOI technology. He is experienced in device and small circuit design, process integration, electrical characterization and compact modeling, both in industrial and academic contexts (STMicroelectronics, IMEP-LAHC, CEA-LETI). His research applications include neuromorphic computing, silicon spin qubit quantum computing and cryo-CMOS circuit design. Since 2021, he is one of the developers of the standard com-pact model PSP and L- UTSOI in the CMC. He is the author and co-authors of more than 20 papers and 10 patents.

Short Courses

Short Course 1: Logic Devices

Session Chair : Prof. Saurabh Lodha

1) Logic Technology Roadmap


Exponential progress in Artificial Intelligence (AI) has been enabled by significant advances in hardware and software technology. The hardware technology roadmap is set by the P.P.A.C.T.R.Y.S metrics of low Power, high Performance, reduced Area, low Cost, fast Time to market, high Reliability, high manufacturing Yield and Sustainability. Achieving continuous improvement in hardware requires seamless synergy between its building blocks of logic, memory, packaging, and networking.

During this short course, lets focus on the logic technology roadmap. We will explore the current state of transistor and interconnect, review materials/process/equipment challenges and delve into emerging technologies for next-generation low-power, high-performance computing. With FinFET scaling approaching its limits, innovative device architectures emerge as promising candidates for next-generation transistor technology, including Gate-All-Around (GAA), Complementary FET (CFET). To address large wire delay and the high IR drop issue resulting from continuous area scaling, novel interconnect material and innovative integration schemes like Backside Power Delivery Network (BSPDN) have been developed.

We will also discuss why technology roadmap follows a 'perseverant tortoise' approach and how we can expedite this.

Gaurav Thareja (Applied Materials, USA)

  • Gaurav Thareja is Director and Head of Process Integration group for Metals Deposition Products (MDP) at Applied Materials. With Stanford EE PhD, multiple patents/publications/invited talks, he has fifteen years of experience in the semiconductor industry at Startup, Intel, Texas Instruments and ST Microelectronics. His favorite quote is from Charles Darwin, “It is not the strongest of the species that survive, not the most intelligent that survives. It is the one that is most adaptable to change.”

2) Nanosheet-based Transistor Architectures for Advanced CMOS Scaling


CMOS scaling is entering the Nanosheet Era. The first generations of Gate-All- Around (GAA) nanosheet-based transistors are being introduced in advanced CMOS production technologies, while research and development of the next generations are in full swing. Multiple scaling opportunities beyond the capabilities of the first nanosheet transistor generations have been identified, but for turning these opportunities into reality, a wide range of integration and process challenges need to be addressed.

This short course covers various aspect of nanosheet-based transistor fabrication. The basic building blocks of GAA nanosheet fabrication will be visualized by 3D animations. Subsequently, potential solutions to either place nanosheet-based transistors closer to each other (Forksheet) or stacking them on top of each other (CFET) will be described. Recent progress in the fabrication of these types of transistors will be discussed, covering front-end- of-line and middle-of-line innovations.

Hans Mertens (IMEC, Belgium )

  • Hans Mertens received a M.S. Degree in applied physics from Eindhoven University of Technology (2002) and a Ph.D degree in physics from Utrecht University (2007), both in The Netherlands. From 2007 to 2012 he was a senior scientist at NXP Semiconductors, working on SiGe heterojunction bipolar transistors for RF applications. He joined imec in 2012, where he is a principal member of technical staff. In this role, he focuses on exploring novel integration solutions for advanced CMOS transistor architectures, including nanosheet FETs, forksheet FETs, and CFETs.

Short Course 2: Advanced Memory Technologies (AMT)

Session Chair : Prof. Udayan Ganguly

1) DRAM Scaling: History and Evolution


With the advent of the Fourth Industrial Revolution, there is a rapid increase in demand for both capacity and performance in DRAM memory. In this course, we will introduce the history of DRAM Cell technology evolution that has challenged and evolved for DRAM scaling to increase capacity so far. We will also discuss the future directions of scaling technology and address topics such as overcoming data sensing margin challenges and the DRAM peripheral transistor technology challenges for achieving high performance of graphic DRAMs (GDDR) and high-band width memories (HBM) for AI servers in the era of sub-15nm deep scaling.

Sung Ho Jang (Samsung Electronics)

  • Sung Ho Jang received the BS, MS and Ph.D. degree in material science and engineering from the Seoul National University, Seoul, Korea, in 1998, 2000 and 2003 respectively. His Ph. D. thesis focused on the magnetoresistance characterization of spin vales and magnetic tunnel transistors for spintronic devices. After completing his Ph.D. degree, he joined Samsung electronics in 2003, as a process architecture engineer for DRAM devices. Since 2010, he has been charged of high performance DRAM devices integration projects for DRAM application, such as high-k metal gate technologies and high-band width memories. His current research activities encompass the performance development of the cell and peripheral transistors as a device engineering project leader in the DRAM development team, Semiconductor R&D Center.

3) Introduction to DRAM and NAND Memories - Technology, and Design Perspectives


In this short course, we will cover the fundamentals of the NAND and DRAM memories. We will examine the basics of technology and the devices associated with these memories. We will then look at the considerations of scaling and design that provide exciting opportunities to create next generation memory systems.

Partha Parthasarathy (Micron)

Short Course 3: Packaging and Heterogeneous Integration (PHI)

Session Chair : Prof. Shree Prakash Tiwari

1) Recent Advancements in Interconnect Materials and Technologies in Semiconductor Packaging


This short course will cover the advancement in both the first level interconnects (FLI) and second level interconnects (SLI) in semiconductor packaging. The FLIs have evolved from an older generation techniques like wire bonding to flip chip using solder to solderless direct copper to copper hybrid bonding enabling sub-10 mm pitch with significant improvement in the performance. The course will also highlight the progress in the SLI connections with a case study on low temperature solders for board level assembly.

Nilesh Badwe (IIT Kanpur)

  • Nilesh Badwe is an Assistant Professor in the Department of Materials Science and Engineering at IIT Kanpur. He obtained his B.Tech. from IIT Bombay in 2008 and Ph.D. from Arizona State University in 2014. Later he worked in Intel Corporation, USA as a Materials Technologist and Staff Packaging R&D Engineer before joining IIT Kanpur in 2021. Nilesh is an Associate Editor for the Journal Microelectronics Reliability. He is also Technical chair for the India Semiconductor and Packaging Ecosystem Conference and chair for the Packaging and Heterogeneous Integration Track at IEEE EDTM 2024.

2) Fan Out Semiconductor Packaging: Evolution, Current Status and Future Trends

Santosh Kumar (Reliance Industries Limited)