FDIP Workshop
Future Directions in IC and Package Design Workshop
- Presentations from FDIP '10 workshop
- Thinking in 3D, Improving perfornamce and modularity
- A Novel Embedded Common-mode Filter for above GHz differential signals based on Metamaterial concept
- 3D Heterogeneous Technologies for Memory-Processor & CMOS-Sensor Stacking
- Signal Integrity Design of TSV-Based 3D IC
- High-Bandwidth Integrated Optics for Server Applications
- Presentations from FDIP '09 workshop
- System Electromagnetic Extraction and Modeling in a Collaborative World
- Future EM Tool Requirements for Industry-Based Hardware Designs
- Preparing for Future System Design Challenges: Advanced Technologies and Integration
- Fast 3D EM Simulation for Digital System Design
- Trends and Requirements for System-Level Design of Signal and Power Delivery
- An Industry-Academic Collaborative Model for EM CAD Research and Development in Packaging
- Accounting for Variability and Uncertainty in Signal and Power Integrity Modeling
- Presentations from FDIP '08 workshop
- Design and Modeling of Through-Silicon Vias for 3D Integration
- Design Considerations for Highly Integrated 3D SiP for Mobile Applications
- Advanced Surface Based MoM Techniques for Packaging and Interconnect Analysis
- Electromagnetic Solvers for Interconnect and Package Modeling - New Developments
- Accelerated, Parallelized Integral Equation Techniques for Packaged Microelectronics
- Presentations from FDIP '07 workshop
- Signal Bandwidth for High-Performance Computing
- Power Delivery System Design Challenges
- Wireless Proximity Communications for 3D System Integration
- Modeling Challenges for Power Distribution Analysis
- A Critical Assessment of the State of the Art in Multiscale Multiphysics Modeling of Microelectronics
- Power Delivery Challenges for the Mobile Platforms
- Presentations from FDIP '06 workshop
- Chip-Multithreading Keeps the Data Center Cool
- Electromagnetic and Circuit Co-Simulation and the Future of IC and Package Design
- Solving the Challenges Posed by Chip/Package/Board Co-Design
- Package Net Group Creation
- Characterizing and Managing Variability in Microprocessor Chips
- Future Directions in Computational Electromagnetics for Digital Applications
- Modeling and Analysis Challenges for Complex Digital Systems-in-Package Designs
- Presentations from FDIP '05 workshop
- Computational Electromagnetics for Circuits Simulations--the Challenges (current_w_gap.mpg)
- Signal Interconnect Trends and Challenges Inside the CEC
- Server Design in a Commodity World
- Electromagnetic Field Visualization System for IC/Package Design Based on Optical Techniques
- Harnessing the Power of Parallel Computation on the IBM BlueGene/L to Analyze Complex Digital and RF Systems
- High Volume Signal and Power Integrity Design for ASICs
- Presentations from FDIP '04 workshop
- Gigascale Integration - Design Challenges and Opportunities
- Emerging Trends in High-Speed Interconnects and Packaging Engineering
- Analog RF CMOS and Optical Design Techniques for 10+ Gbps Datacom
- Power Distribution - Status and Challenges
- Signal Integrity Modeling and Simulation for IC/Package Co-Design
- Current and Future Directions in Simulator Development
- Presentations from FDIP '03 workshop
- BlueGene/L Supercomputer
- Mixed-Signal Measurement Circuits For Embedded Test Access
- CAD Tool Requirements for Next Generation On-Chip Signal Integrity
- Toward Full-Chip Analysis with EM Accuracy
- Clock Distribution for Multi-GHz Microprocessors
- Package Level EMI Study
- The Challenge of Correct Modelling and Testing of Advanced High-Speed Multi-Pin Connectors
- Presentations from FDIP '02 workshop
- Full Chip Analysis
- The Impact of Chip and Package Design on Radiated EMI
- Network Processors
- Optimization of Electrical Package Design and PCB Design for CSP Age
- Presentations from FDIP '01 workshop
- Coupled Interference in Mixed Signal Wireless ICs and Implications for Package Design
- Integration of RF passive elements in telecommunication
- Next-Generation System Design Challenges and Opportunities
- Wafer level Stacking